Datasheet

DS26521 Single T1/E1/J1 Transceiver
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NAME PIN TYPE FUNCTION
TSYNC 61 I/O
Transmit Synchronization. A pulse at this pin establishes either frame or
multiframe boundaries for the transmit side. This signal can also be programmed to
output either a frame or multiframe pulse. If this pin is set to output pulses at frame
boundaries, it can also be set to output double-wide pulses at signaling frames in
T1 mode. The operation of this signals is synchronous with TCLK.
TSSYNCIO 60 I/O
Transmit System Synchronization In. Only used when the transmit-side elastic
store is enabled. A pulse at this pin establishes either frame or multiframe
boundaries for the transmit side. Note that if the elastic store is enabled, frame or
multiframe boundary will be established for the transmitter. Should be tied low in
applications that do not use the transmit-side elastic store. The operation of this
signal is synchronous with TSYSCLK.
Transmit System Synchronization Out. If configured as an output, an 8kHz
pulse synchronous to the BPCLK will be generated. This pulse in combination with
BPCLK can be used as an IBO master. The BPCLK can be sourced to RSYSCLK,
TSYSCLK, and TSSYNCIO as a source to RSYNC, and TSSYNCIO of DS26521
or RSYNC and TSSYNC of other Dallas Semiconductor parts.
TSIG 59
I
Transmit Signaling. When enabled, this input samples signaling bits for insertion
into outgoing PCM data stream. Sampled on the falling edge of TCLK when the
transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK
when the transmit-side elastic store is enabled.
TCHBLK/
CLK
58 O
Transmit Channel Block/Transmit Channel Block Clock. A dual function pin.
TCHBLK is a user-programmable output that can be forced high or low. It is
synchronous with TCLK when the transmit-side elastic store is disabled. It is
synchronous with TSYSCLK when the transmit-side elastic store is enabled. It is
useful for blocking clocks to a serial UART or LAPD controller in applications
where not all channels are used such as Fractional T1, Fractional E1, 384kbps
(H0), 768kbps, or ISDN-PRI. Also useful for locating individual channels in drop-
and-insert applications, for external per-channel loopback, and for per-channel
conditioning.
TCHCLK. TCHCLK is a 192kHz (T1) or 256kHz (E1) clock that pulses high during
the LSB of the channel. It can also be programmed to output a gated transmit bit
clock controlled by TCHBLK. It is synchronous with TCLK when the transmit-side
elastic store is disabled. It is synchronous with TSYSCLK when the transmit-side
elastic store is enabled. Useful for parallel-to-serial conversion of channel data.