Datasheet

DS26521 Single T1/E1/J1 Transceiver
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Register Name:
TRTS2
Register Description:
Transmit Real-Time Status Register 2 (HDLC)
Register Address:
1B1h
Bit # 7 6 5 4 3 2 1 0
Name — — — — TEMPTY TFULL TLWM TNF
Default 0 0 0 0 0 0 0 0
Note: All bits in this register are real time.
Bit 3: Transmit FIFO Empty (TEMPTY). A real-time bit that is set high when the FIFO is empty.
Bit 2: Transmit FIFO Full (TFULL). A real-time bit that is set high when the FIFO is full.
Bit 1: Transmit FIFO Below Low Watermark Condition (TLWM). Set when the transmit 64-byte FIFO empties
beyond the low watermark as defined by the transmit low watermark bits (TLWM).
Bit 0: Transmit FIFO Not Full Condition (TNF). Set when the transmit 64-byte FIFO has at least one byte
available.
Register Name:
TFBA
Register Description:
Transmit HDLC FIFO Buffer Available
Register Address:
1B3h
Bit # 7 6 5 4 3 2 1 0
Name — TFBA6 TFBA5 TFBA4 TFBA3 TFBA2 TFBA1 TFBA0
Default 0 0 0 0 0 0 0 0
Bits 6 to 0: Transmit FIFO Bytes Available (TFBA[6:0]). TFBA0 is the LSB.
Register Name:
THF
Register Description:
Transmit HDLC FIFO Register
Register Address:
1B4h
Bit # 7 6 5 4 3 2 1 0
Name THD7 THD6 THD5 THD4 THD3 THD2 THD1 THD0
Default 0 0 0 0 0 0 0 0
Bit 7: Transmit HDLC Data Bit 7 (THD7). MSB of an HDLC packet data byte.
Bit 6: Transmit HDLC Data Bit 6 (THD6).
Bit 5: Transmit HDLC Data Bit 5 (THD5).
Bit 4: Transmit HDLC Data Bit 4 (THD4).
Bit 3: Transmit HDLC Data Bit 3 (THD3).
Bit 2: Transmit HDLC Data Bit 2 (THD2).
Bit 1: Transmit HDLC Data Bit 1 (THD1).
Bit 0: Transmit HDLC Data Bit 0 (THD0). LSB of an HDLC packet data byte.