Datasheet

DS26521 Single T1/E1/J1 Transceiver
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Register Name:
TIM2
Register Description:
Transmit Interrupt Mask Register 2 (HDLC)
Register Address:
1A1h
Bit # 7 6 5 4 3 2 1 0
Name — — — TFDLE TUDR TMEND TLWMS TNFS
— — — —
TUDR TMEND TLWMS TNFS
Default 0 0 0 0 0 0 0 0
Bit 4: Transmit FDL Register Empty (TFDLE) (T1 Mode Only).
0 = interrupt masked
1 = interrupt enabled
Bit 3: Transmit FIFO Underrun Event (TUDR).
0 = interrupt masked
1 = interrupt enabled
Bit 2: Transmit Message End Event (TMEND).
0 = interrupt masked
1 = interrupt enabled
Bit 1: Transmit FIFO Below Low Watermark Set Condition (TLWMS).
0 = interrupt masked
1 = interrupt enabled
Bit 0: Transmit FIFO Not Full Set Condition (TNFS).
0 = interrupt masked
1 = interrupt enabled
Register Name:
TIM3
Register Description:
Transmit Interrupt Mask Register 3 (Synchronizer)
Register Address:
1A2h
Bit # 7 6 5 4 3 2 1 0
Name — — — — — — — LOFD
Default 0 0 0 0 0 0 0 0
Bit 0: Loss of Frame Synchronization Detect (LOFD).
0 = interrupt masked
1 = interrupt enabled