Datasheet

DS26521 Single T1/E1/J1 Transceiver
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Register Name:
TIM1
Register Description:
Transmit Interrupt Mask Register 1
Register Address:
1A0h
Bit # 7 6 5 4 3 2 1 0
Name TESF TESEM TSLIP TSLC96 TPDV TMF LOTCC LOTC
TESF TESEM TSLIP
—
TAF TMF LOTCC LOTC
Default 0 0 0 0 0 0 0 0
Bit 7: Transmit Elastic Store Full Event (TESF).
0 = interrupt masked
1 = interrupt enabled
Bit 6: Transmit Elastic Store Empty Event (TESEM).
0 = interrupt masked
1 = interrupt enabled
Bit 5: Transmit Elastic Store Slip Occurrence Event (TSLIP).
0 = interrupt masked
1 = interrupt enabled
Bit 4: Transmit SLC-96 Multiframe Event (TSLC96) (T1 Mode Only).
0 = interrupt masked
1 = interrupt enabled
Bit 3 (T1 Mode): Transmit Pulse Density Violation Event (TPDV).
0 = interrupt masked
1 = interrupt enabled
Bit 3 (E1 Mode): Transmit Align Frame Event (TAF).
0 = interrupt masked
1 = interrupt enabled
Bit 2: Transmit Multiframe Event (TMF).
0 = interrupt masked
1 = interrupt enabled
Bit 1: Loss of Transmit Clock Clear Condition (LOTCC).
0 = interrupt masked
1 = interrupt enabled
Bit 0: Loss of Transmit Clock Condition (LOTC).
0 = interrupt masked
1 = interrupt enabled