Datasheet

DS26521 Single T1/E1/J1 Transceiver
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Figure 6-2. Detailed Block Diagram
DS26521
TRANSMIT
LIU
Waveform
Shaper/Line
Driver
RECEIVE
LIU
Clock/Data
Recovery
JITTER ATTENUATOR
TRANSMIT
ENABLE
Tx
BERT
Rx
BERT
Tx
HDLC
Rx
HDLC
Tx FRAMER:
System IF
B8ZS/
HDB3
Encode
Elastic
Store
Rx FRAMER:
System IF
B8ZS/
HDB3
Decode
Elastic
Store
BACKPLANE INTERFACE
ALB
LLB
FLB
RLB
PLB
BACKPLANE
CLOCK
GENERATOR
MICROPROCESSOR
INTERF
A
CE
JTAG
PORT
RESET
BLOCK
A
12,[8:0]
D[7:0]
C
SB
R
DB/DSB
W
RB/RWB
BTS
I
NTB
JTDI JTMS JTCLK JTDO
J
TRST
R
ESETB
MCLK
RCHBLK/CLK
TCHBLK/CLK
TCLK
TSER
TSYNC
TSYSCLK
RSYSCLK
RSYNC
RSER
RCLK
BPCLK
REFCLK
TSSYNCIO
(Output Mode)
TTIP
TRING
RRING
RTIP
DS26522
TSSYNCIO
(Input Mode)
Serial Interface Mode:
SPI
(SCLK, CPOL, CPHA,
SWAP, MOSI, and MISO)
RSIG
RM/RFSYNC
A
L/RSIGF/FLOS
RLF/LTC
TSIG
PRE-SCALER
PLL
SPI_SEL