Datasheet

DS26521 Single T1/E1/J1 Transceiver
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6. BLOCK DIAGRAMS
Figure 6-1. Block Diagram
DS26521
T1/E1 FRAMER
HDLC
BERT
MICRO PROCESSOR
INTERFACE
JTAG PORT
CLOCK
GENERATION
LINE
INTERFACE
UNIT
BACKPLANE
INTERFACE
ELASTIC
STORES
RTIP
TRING
RRING
TTIP
CONTROLLER
PORT
TEST
PORT
CLOCK
ADAPTER
RECEIVE
BACKPLANE
SIGNALS
TRANSMIT
BACKPLANE
SIGNALS
HARDWARE
A
LARM
INDICATORS