Datasheet

DS26521 Single T1/E1/J1 Transceiver
162 of 258
Register Name:
RRTS3 (T1 Mode)
Register Description:
Receive Real-Time Status Register 3
Register Address:
0B2h
Bit # 7 6 5 4 3 2 1 0
Name — — — — LORC LSP LDN LUP
Default 0 0 0 0 0 0 0 0
Note: All bits in this register are real-time (not latched). See RRTS3 for E1 mode.
Bit 3: Loss of Receive Clock Condition (LORC). Set when the RCLK pin has not transitioned for one channel
time.
Bit 2: Spare Code Detected Condition (LSP). Set when the spare code as defined in the
T1RSCD1:T1RSCD2
registers is being received.
Bit 1: Loop-Down Code Detected Condition (LDN). Set when the loop-down code as defined in the
T1RDNCD1:T1RDNCD2 register is being received.
Bit 0: Loop-Up Code Detected Condition (LUP). Set when the loop-up code as defined in the
T1RUPCD1:T1RUPCD2 register is being received.
Register Name:
RRTS3 (E1 Mode)
Register Description:
Receive Real-Time Status Register 3
Register Address:
0B2h
Bit # 7 6 5 4 3 2 1 0
Name — — — — LORC — V52LNK RDMA
Default 0 0 0 0 0 0 0 0
Note: All bits in this register are real-time (not latched). See RRTS3 for T1 mode.
Bit 3: Loss of Receive Clock Condition (LORC). Set when the RCLK pin has not transitioned for one channel
time.
Bit 1: V5.2 Link Detected Condition (V52LNK). Set on detection of a V5.2 link identification signal (G.965).
Bit 0: Receive Distant MF Alarm Condition (RDMA). Set when bit 6 of time slot 16 in frame 0 has been set for
two consecutive multiframes. This alarm is not disabled in the CCS signaling mode.