Datasheet

DS26521 Single T1/E1/J1 Transceiver
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Register Name:
RIIR
Register Description:
Receive Interrupt Information Register
Register Address:
09Fh
Bit # 7 6 5 4 3 2 1 0
Name — RLS7 RLS6* RLS5 RLS4 RLS3 RLS2** RLS1
Default 0 0 0 0 0 0 0 0
*RLS6 is reserved for future use.
**Currently, RLS2 does not create an interrupt, therefore this bit is not used in T1 mode.
The Receive Interrupt Information register (
RIIR) indicates which of the DS26521 status registers are generating an
interrupt. When an interrupt occurs, the host can read RIIR to quickly identify which of the receive status registers
is (are) causing the interrupt(s). The RIIR bits clear once the appropriate interrupt has been serviced and cleared,
as long as no additional, unmasked interrupt condition is present in the associated status register. Status bits that
have been masked via the Receive Interrupt Mask (RIMx) registers will also be masked from the RIIR register.
Register Name:
RIM1
Register Description:
Receive Interrupt Mask Register 1
Register Address:
0A0h
Bit # 7 6 5 4 3 2 1 0
Name RRAIC RAISC RLOSC RLOFC RRAID RAISD RLOSD RLOFD
Default 0 0 0 0 0 0 0 0
Bit 7: Receive Remote Alarm Indication Condition Clear (RRAIC).
0 = interrupt masked
1 = interrupt enabled
Bit 6: Receive Alarm Indication Signal Condition Clear (RAISC).
0 = interrupt masked
1 = interrupt enabled
Bit 5: Receive Loss of Signal Condition Clear (RLOSC).
0 = interrupt masked
1 = interrupt enabled
Bit 4: Receive Loss of Frame Condition Clear (RLOFC).
0 = interrupt masked
1 = interrupt enabled
Bit 3: Receive Remote Alarm Indication Condition Detect (RRAID).
0 = interrupt masked
1 = interrupt enabled
Bit 2: Receive Alarm Indication Signal Condition Detect (RAISD).
0 = interrupt masked
1 = interrupt enabled
Bit 1: Receive Loss of Signal Condition Detect (RLOSD).
0 = interrupt masked
1 = interrupt enabled
Bit 0: Receive Loss of Frame Condition Detect (RLOFD).
0 = interrupt masked
1 = interrupt enabled