Datasheet

DS26521 Single T1/E1/J1 Transceiver
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Register Name:
RSS1, RSS2, RSS3, RSS4
Register Description:
Receive-Signaling Status Registers 1 to 4
Register Address:
098h, 099h, 09Ah, 09Bh
Bit # (MSB) 7 6 5 4 3 2 1 0 (LSB)
Name CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1*
RSS1
CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
RSS2
CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17*
RSS3
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
RSS4
(E1 Mode
Only)
Default 0 0 0 0 0 0 0 0
Note: Status bits in this register are latched.
When a channel’s signaling data changes state, the respective bit in registers
RSS1:RSS4 will be set and latched.
The RSCOS bit (
RLS4.3) will be set if the channel was also enabled by setting the appropriate bit in RSCSE1:4.
The INTB signal will go low if enabled by the interrupt mask bit
RIM4.3. The bit will remain set until read.
*
Note that in E1 CAS mode, the LSB of RSS1 would typically represent the CAS alignment bits, and the LSB of RSS3
represents reserved bits and the distant multiframe alarm.