Datasheet

DS26521 Single T1/E1/J1 Transceiver

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9.4 Framer Register Definitions

See Table 9-3 for the complete framer register list.

9.4.1 Receive Register Definitions

RHC

Receive HDLC Control Register

010h

Bit # 7 6 5 4 3 2 1 0

Name RCRCD RHR RHMS RHCS4 RHCS3 RHCS2 RHCS1 RHCS0

Default 0 0 0 0 0 0 0 0

Bit 7: Receive CRC-16 Display (RCRCD).

0 = Do not write received CRC-16 code to FIFO (default)

1 = Write received CRC-16 code to FIFO after last octet of packet

Bit 6: Receive HDLC Reset (RHR). Will reset the receive HDLC controller and flush the receive FIFO. Note that

this bit is a acknowledged reset. The host should set this bit and the DS26521 will clear it once the reset operation

is complete. The DS26521 will complete the HDLC reset within two frames.

0 = Normal operation

1 = Reset receive HDLC controller and flush the receive FIFO

Bit 5: Receive HDLC Mapping Select (RHMS).

0 = Receive HDLC assigned to channels

1 = Receive HDLC assigned to FDL (T1 mode), Sa bits (E1 mode)

Bit 4 to 0: Receive HDLC Channel Select 4 to 0 (RHCS[4:0]). These bits determine which DS0 is mapped to the

HDLC controller when enabled with RHMS = 0. RHCS[4:0] = all 0s selects channel 1, RHCS[4:0] = all 1s selects

channel 32 (E1). A change to the receive HDLC channel select is acknowledged only after a receive HDLC reset

(RHR).