Datasheet
DS26521 Single T1/E1/J1 Transceiver
104 of 258
Register Name:
GTCCR
Register Description:
Global Transceiver Clock Control Register
Register Address:
0F3h
Read/Write Function
R/W
Bit # 7 6 5 4 3 2 1 0
Name
BPREFSEL3 BPREFSEL2 BPREFSEL1 BPREFSEL0 BFREQSEL FREQSEL MPS1 MPS0
Default 0 0 0 0 0 0 0 0
Bits 7 to 4: Backplane Clock Reference Selects (BPREFSEL[3:0]).These bits select which reference clock
source will be used for BPCLK generation. The BPCLK can be generated from the LIU recovered clock, an external
reference, or derivatives of MCLK input. This is shown in
Table 9-11. See Figure 8-9 for additional information.
Bit 3: Backplane Frequency Select (BFREQSEL). In conjunction with BPRFSEL[3:0], this bit identifies the
reference clock frequency used by the DS26521 backplane clock generation circuit. Note that the setting of this bit
should match the T1E1 selection for the LIU whose recovered clock is being used to generate the backplane clock.
See
Figure 8-9 for additional information.
0 = Backplane reference clock is 2.048MHz.
1 = Backplane reference clock is 1.544MHz.
Bit 2: Frequency Selection (FREQSEL). In conjunction with the MPS[1:0] bits, this bit selects the external MCLK
frequency of the signal input at the MCLK pin of the DS26521.
0 = The external master clock is 2.048MHz or multiple thereof.
1 = The external master clock is 1.544MHz or multiple thereof.
Bits 1 and 0: Master Period Select 1 and 0 (MPS[1:0]). In conjunction with the FREQSEL bit, these bits select
the external MCLK frequency of the signal input at the MCLK pin of the DS26521. This is shown in
Table 9-12.
Table 9-11. Backplane Reference Clock Select
BPREFSEL3 BPREFSEL2 BPREFSEL1 BPREFSEL0 BFREQSEL
REFERENCE CLOCK
SOURCE
0 0 0 0 0 2.048MHz RCLK
0 0 0 0 1 1.544MHz RCLK
1 0 0 0 1
1.544MHz derived from MCLK. (REFCLKIO is an
output.)
1 0 0 1 0
2.048MHz derived from MCLK. (REFCLKIO is an
output.)
1 0 1 0 0
2.048MHz external clock input at REFCLKIO.
(REFCLKIO is an input.)
1 0 1 0 1
1.544MHz external clock input at REFCLKIO.
(REFCLKIO is an input.)
Table 9-12. Master Clock Input Selection
FREQSEL MPS1 MPS0
MCLK
(MHz ±50ppm)
0 0 0 2.048
0 0 1 4.096
0 1 0 8.192
0 1 1 16.384
1 0 0 1.544
1 0 1 3.088
1 1 0 6.176
1 1 1 12.352