Datasheet
DS26521 Single T1/E1/J1 Transceiver
103 of 258
Register Name:
GFCR
Description:
Global Framer Control Register
Register Address:
0F1h
Bit # 7 6 5 4 3 2 1 0
Name — — BPCLK1 BPCLK0 RFLOSSFS RFMSS TCBCS RCBCS
Default 0 0 0 0 0 0 0 0
Bits 5 and 4: Backplane Clock Select 1 and 0 (BPCLK[1:0]). These bits determine the clock frequency output on
the BPCLK pin.
BPCLK1 BPCLK0 BPCLK FREQUENCY
0 0 2.048MHz
0 1 4.096MHz
1 0 8.192MHz
1 1 16.384MHz
Bit 3: Receive Loss of Signal/Signaling Freeze Select (RLOSSFS). This bit controls the function of the
AL/RSIGF/FLOS pin. The receive LOS is further selected between framer LOS and LIU LOS by
GTCR2.2.
0 = AL/RSIGF/FLOS pin outputs RLOS (receive loss)
1 = AL/RSIGF/FLOS pin outputs RSIGF (receive-signaling freeze)
Bit 2: Receive Frame/Multiframe Sync Select (RFMSS). This bit controls the function of the RMSYNC/RFSYNC
pin.
0 = RMSYNC/RFSYNC pin outputs RFSYNC (receive frame sync)
1 = RMSYNC/RFSYNC pin outputs RMSYNC (receive multiframe sync)
Bit 1: Transmit Channel Block/Clock Select (TCBCS). This bit controls the function of the TCHBLK/CLK pin.
0 = TCHBLK/CLK pin outputs TCHBLK (transmit channel block)
1 = TCHBLK/CLK pin outputs TCHCLK (transmit channel clock)
Bit 0: Receive Channel Block/Clock Select (RCBCS). This bit controls the function of the RCHBLK/CLK pin.
0 = RCHBLK/CLK pin outputs RCHBLK (receive channel block)
1 = RCHBLK/CLK pin outputs RCHCLK (receive channel clock)
Register Name:
GTCR2
Register Description:
Global Transceiver Control Register 2
Register Address:
0F2h
Bit # 7 6 5 4 3 2 1 0
Name — — — — — LOSS TSSYNCIOSEL —
Default 0 0 0 0 0 0 0 0
Bit 2: LOS Selection (LOSS). If this bit is set, the AL/RSIGF/FLOS pin can be driven with LIU loss. If reset, the
pins can be driven by framer LOS. The selection of whether to drive AL/RSIGF/FLOS pin with LOS (analog or
digital) or signalling freeze is controlled by
GFCR.2.
Bit 1: Transmit System Synchronization I/O Select (TSSYNCIOSEL). If this bit is set to a 1, the TSSYNCIO is
an 8kHz output synchronous to the BPCLK. This “frame pulse” can be used in conjunction with the backplane clock
to provide IBO signals for a system backplane. If this bit is reset, TSSYNCIO is an input. An 8kHz frame pulse is
required for transmit synchronization and IBO operation.