Datasheet

DS26521 Single T1/E1/J1 Transceiver
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9.3 Global Register Definitions
Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status,
framer interrupt status, IBO configuration, MCLK configuration, and BPCLK configuration. The global registers bit
descriptions are presented in this section.
Table 9-10. Global Register Set
ADDRESS NAME DESCRIPTION R/W
0F0h GTCR1 Global Transceiver Control Register 1 R/W
0F1h GFCR Global Framer Control Register R/W
0F2h GTCR2 Global Transceiver Control Register 2 R/W
0F3h GTCCR Global Transceiver Clock Control Register R/W
0F4h — Reserved —
0F5h GLSRR Global LIU Software Reset Register R/W
0F6h GFSRR Global Framer and BERT Software Reset Register R/W
0F7h — Reserved —
0F8h IDR Device Identification Register R
0F9h GFISR Global Framer Interrupt Status Register R
0FAh GBISR Global BERT Interrupt Status Register R
0FBh GLISR Global LIU Interrupt Status Register R
0FCh GFIMR Global Framers Interrupt Mask Register R/W
0FDh GBIMR Global BERT Interrupt Mask Register R/W
0FEh GLIMR Global LIU Interrupt Mask Register R/W
01Fh — Reserved —
Note 1: Reserved registers should only be written with all zeros.
Note 2: The global registers are located in the framer address space.