Datasheet
DS26518 8-Port T1/E1/J1 Transceiver
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9.12.1 LIU Operation
The analog AMI/HDB3 waveforms off of the E1 lines or the AMI/B8ZS waveform off of the T1 lines are transformer
coupled into the RTIPn and RRINGn pins of the DS26518. The user has the option to use internal termination,
software selectable for 75Ω/100Ω/110Ω/120Ω applications, or external termination. The LIU recovers clock and
data from the analog signal and passes it through the jitter attenuation mux. The DS26518 contains an active filter
that reconstructs the analog received signal for the nonlinear losses that occur in transmission. The receive
circuitry also is configurable for various monitor applications. The device has a usable receive sensitivity of 0dB to
-43dB for E1 and 0dB to -36dB for T1, which allows the device to operate on 0.63mm (22AWG) cables up to 2.5km
(E1) and 6k feet (T1) in length. Data input to the transmit side of the LIU is sent via the jitter attenuation mux to the
wave shaping circuitry and line driver. The DS26518 will drive the E1 or T1 line from the TTIPn and TRINGn pins
via a coupling transformer. The line driver can handle both CEPT 30/ISDN-PRI lines for E1 and long-haul (CSU) or
short-haul (DSX-1) lines for T1. The registers that control the LIU operation are shown in
Table 9-40.
Table 9-40. Registers Related to Control of the LIU
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Global Transceiver Clock Control Register 1
(
GTCCR1)
00F3h
MPS selections, backplane clock
selections.
Global Software Reset Register 1 (GSRR1) 00F6h Software reset control for the LIU.
Global LIU Interrupt Status Register 1 (GLISR1) 00FBh
Interrupt status bit for each of the eight
LIUs.
Global LIU Interrupt Mask Register 1 (GLIMR1) 00FEh Interrupt mask register for the LIU.
LIU Transmit Receive Control Register (LTRCR) 1000h
T1/J1/E1 selection, output tri-state, loss
criteria.
LIU Transmit Impedance and Pulse Shape
Selection Register (
LTIPSR)
1001h
Transmit pulse shape and impedance
selection.
LIU Maintenance Control Register (LMCR) 1002h
Transmit maintenance and jitter
attenuation control register.
LIU Real Status Register (LRSR) 1003h LIU real-time status register.
LIU Status Interrupt Mask Register (LSIMR) 1004h
LIU mask registers based on latched
status bits.
LIU Latched Status Register (LLSR) 1005h
LIU latched status bits related to loss, open
circuit, etc.
LIU Receive Signal Level Register (LRSL) 1006h LIU receive signal level indicator.
LIU Receive Impedance and Sensitivity Monitor
Register (
LRISMR)
1007h
LIU impedance match and sensitivity
monitor.
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex), where n = 2 to 8 for Framers 2 to 8.