Datasheet

DS26518 8-Port T1/E1/J1 Transceiver
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9.10.3.4 Transmit HDLC-256 Example
The HDLC-256 status registers in the DS26518 allow for flexible software interface to meet the user’s preferences.
When transmitting HDLC-256 messages, the host can choose to be interrupt driven or to poll to desired status
registers, or a combination of polling and interrupt processes can be used.
Figure 9-20 shows an example routine
for using the DS26518 HDLC-256 receiver.
Figure 9-20. Transmit HDLC-256 Message Example
Configure Transmit
HDLC-256 Controller
(TH256CR1,2)
Write TH256FDR1, 2;
N = 8xTDAL -1
Read TH256SRL
exit
Enable Interrupt
(THDA)
Reset FIFO
(TH256CR1.TFRST)
INTB Active?
THDAL Set?
exit
N = 0 ?
Write TH256FDR1, 2;
N = N -1
YES
NO
NO
NO
YES
YES
exit
Packet End?
YES
exit
NO