Datasheet

DS26518 8-Port T1/E1/J1 Transceiver
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9.10.3.3 Receive HDLC-256 Example
The HDLC-256 status registers in the DS26518 allow for flexible software interface to meet the user’s preferences.
When receiving HDLC-256 messages, the host can choose to be interrupt driven or to poll to desired status
registers, or a combination of polling and interrupt processes can be used.
Figure 9-19 shows an example routine
for using the DS26518 HDLC-256 receiver.
Figure 9-19. Receive HDLC-256 Message Example
Configure Receive
HDLC-256 Controller
(RH256CR1,2)
Read RH256FDR1,2
until end of packet
reached
Read RH256FDR1, 2;
N = 8xRDAL -1
Read RH256SRL
exit
Enable Interrupts
(RHDAIE, RPEIE)
Reset FIFO
(RH256CR1.RFRST)
INTB Active?
RHDAL Set? RPE Set? exit
N = 0 ? exit
Read RH256FDR1, 2;
N = N -1
YES
NO
NONO
NO
YES
YES