Datasheet

DS26518 8-Port T1/E1/J1 Transceiver
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9.10.3 HDLC-256 Controller
This device has an enhanced HDLC controller that can be mapped into up to 32 time slots, or Sa4 to Sa8 bits (E1
mode), or the FDL (T1 mode). This HDLC controller has a 256-byte FIFO buffer in both the transmit and receive
paths. The user can select any specific bits within the time slot(s) to assign to the HDLC-256 controller as well as
specific Sa bits (E1 mode).
The HDLC-256 controller performs all the necessary overhead for generating and receiving performance report
messages (PRMs) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The
HDLC-256 controller automatically generates and detects flags, generates and checks the CRC checksum,
generates and detects abort sequences, stuffs and destuffs zeros, and byte aligns to the data stream. The
256-byte buffers in the HDLC-256 controller are large enough to allow a full PRM to be received or transmitted
without host intervention. They are also large enough to store an entire frame’s worth of data before requiring host
intervention.
Table 9-38 shows the registers related to the HDLC-256.
Table 9-38. Registers Related to the HDLC-256
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Receive Expansion Port Control Register
(HDLC-256) (
RXPC)
08Ah
Mapping of the HDLC-256 to time slots or FDL,
Sa bits.
Receive HDLC-256 Channel Select
Registers 1 to 4(
RHCS1–RHCS4)
0DCh, 0DDh, 0DEh,
0DFh
Selection of time slots to map data to the
HDLC-256 port.
Receive HDLC-256 Bit Suppress Register
(
RHBS)
08Dh Receive HDLC-256 bit suppression register.
Receive HDLC-256 Control Register 1
(
RH256CR1)
1510h Receive miscellaneous control.
Receive HDLC-256 Control Register 2
(
RH256CR2)
1511h Receive HDLC-256 FIFO data level available.
Receive HDLC-256 Status Register
(
RH256SR)
1514h Indicates the FIFO status.
Receive HDLC-256 FIFO Data Registers
1 and 2 (
RH256FDR1 and RH256FDR2)
151Ch, 151Dh The actual FIFO data.
Transmit Expansion Port Control Register
(
TXPC)
18Ah
Mapping of the HDLC-256 to time slots or FDL,
Sa bits.
Transmit HDLC-256 Channel Select
Registers 1 to 4 (
THCS1–THCS4)
1DCh, 1DDh, 1DEh,
1DFh
Selection of time slots to map data from the
HDLC-256 port.
Transmit HDLC-256 Bit Suppress
Register (
THBS)
18Dh
Transmit HDLC-256 bit suppress for bits not to
be used.
Transmit HDLC-256 Control Register 1
(
TH256CR1)
1500h Transmit miscellaneous control.
Transmit HDLC-256 Control Register 2
(
TH256CR2)
1501h
Indicates the number of bytes that can be
written into the transmit FIFO.
Transmit HDLC-256 FIFO Data Registers
1 and 2 (
TH256FDR1 and TH256FDR2)
1502h, 1503h Transmit HDLC-256 FIFO.
Transmit HDLC-256 Status Registers 1
and 2 (
TH256SR1 and TH256SR2)
1504h, 1505h
Indicates the real-time status of the transmit
HDLC-256 FIFO.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex); where n = 2 to 8 for Framers 2 to 8.