Datasheet

DS26518 8-Port T1/E1/J1 Transceiver
75 of 312
Table 9-37. Registers Related to the HDLC-64
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Receive HDLC-64 Control Register (RHC) 010h
Mapping of the HDLC-64 to DS0 or FDL, Sa
bits.
Receive HDLC-64 Bit Suppress Register
(
RHBSE)
011h Receive HDLC-64 bit suppression register.
Receive HDLC-64 FIFO Control Register
(
RHFC)
087h
Determines the watermark of the receive
HDLC-64 FIFO.
Receive HDLC-64 Packet Bytes Available
Register (
RHPBA)
0B5h
Tells the user how many bytes are available in
the receive HDLC-64 FIFO.
Receive HDLC-64 FIFO Register (RHF) 0B6h The actual FIFO data.
Receive Real-Time Status Register 5
(HDLC-64) (
RRTS5)
0B4h Indicates the FIFO status.
Receive Latched Status Register 5
(HDLC-64) (
RLS5)
094h Latched status.
Receive Interrupt Mask Register 5
(HDLC-64) (
RIM5)
0A4h
Interrupt mask for interrupt generation for the
latched status.
Transmit HDLC-64 Control Register 1 (THC1) 110h Miscellaneous transmit HDLC-64 control.
Transmit HDLC-64 Bit Suppress Register
(
THBSE)
111h
Transmit HDLC-64 bit suppress for bits not to
be used.
Transmit HDLC-64 Control Register 2 (THC2) 113h
HDLC-64 to DS0 channel selection and other
control.
Transmit HDLC-64 FIFO Control Register
(
THFC)
187h Used to control the transmit HDLC-64 FIFO.
Transmit Real-Time Status Register 2
(HDLC-64) (
TRTS2)
1B1h
Indicates the real-time status of the transmit
HDLC-64 FIFO.
Transmit Latched Status Register 2
(HDLC-64) (
TLS2)
191h Indicates the FIFO status.
Transmit Interrupt Mask Register 2
(HDLC-64) (
TIM2)
1A1h Interrupt mask for the latched status.
Transmit HDLC-64 FIFO Buffer Available
Register (
TFBA)
1B3h
Indicates the number of bytes that can be
written into the transmit FIFO.
Transmit HDLC-64 FIFO Register (THF) 1B4h Transmit HDLC-64 FIFO.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex); where n = 2 to 8 for Framers 2 to 8.
9.10.1.1 HDLC-64 FIFO Control
Control of the transmit and receive FIFOs is accomplished via the Receive HDLC-64 FIFO Control (
RHFC) and
Transmit HDLC-64 FIFO Control (
THFC) registers. The FIFO control registers set the watermarks for the FIFO.
When the receive FIFO fills above the high watermark, the RHWM bit (
RRTS5.1) will be set. RHWM and TLWM
are real-time bits and will remain set as long as the FIFO’s write pointer is above the watermark. When the transmit
FIFO empties below the low watermark, the TLWM bit in the
TRTS2 register will be set. TLWM is a real-time bit
and will remain set as long as the transmit FIFO’s write pointer is below the watermark. If enabled, this condition
can also cause an interrupt via the INTB pin.
If the receive HDLC-64 FIFO does overrun the current packet being processed is dropped and the receive FIFO is
emptied. The packet status bits in
RRTS5 and RLS5.5 (ROVR) indicate an overrun.