Datasheet

DS26518 8-Port T1/E1/J1 Transceiver
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9.10 HDLC Controllers
There are two HDLC controllers available for each port of the DS26518. HDLC-64 is the default HDLC controller,
which is software compatible to the entire TEX series of SCTs. The HDLC-256 controller is available on the
DS26518 beginning with die revision B1. (Note: Older DS26518 die revisions do not have this feature, so check
the device errata.)
Table 9-36 describes the features available for each controller.
Table 9-36. HDLC-64/HDLC-256 Controller Features
HDLC
CONTROLLER
FIFO DEPTH
(BYTES)
MAP TO FDL
MAP TO
Sa BITS
MAP TO
SINGLE DS0
MAP TO
MULTIPLE
DS0s
HDLC-64 64 Yes Yes Yes No
HDLC-256 256 Yes Yes Yes Yes, up to 32
9.10.1 HDLC-64 Controller
The DS26518 has an enhanced HDLC controller that can be mapped into a single time slot, or Sa4 to Sa8 bits (E1
mode), or the FDL (T1 mode). This HDLC controller has a 64-byte FIFO buffer in both the transmit and receive
paths. The user can select any specific bits within the time slot(s) to assign to the HDLC-64 controller, as well as
specific Sa bits (E1 mode).
The HDLC-64 controller performs all the necessary overhead for generating and receiving performance report
messages (PRMs) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC-64
controller automatically generates and detects flags, generates and checks the CRC checksum, generates and
detects abort sequences, stuffs and destuffs zeros, and byte aligns to the data stream. The 64-byte buffers in the
HDLC-64 controller are large enough to allow a full PRM to be received or transmitted without host intervention.
Table 9-37 shows the registers related to the HDLC-64.