Datasheet
DS26518 8-Port T1/E1/J1 Transceiver
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9.9.3 T1 Transmit Synchronizer
The DS26518 transmitter can identify the D4 or ESF frame boundary, as well as the CRC multiframe boundaries
within the incoming NRZ data stream at TSERn. The TFM (
TCR3.2) control bit determines whether the transmit
synchronizer searches for the D4 or ESF multiframe. Additional control signals for the transmit synchronizer are
located in the
TSYNCC register. The latched status bit TLS3.0 (LOFD) is provided to indicate that a loss of frame
synchronization has occurred, and a real-time bit (LOF) which is set high when the synchronizer is searching for
frame/multiframe alignment. The LOFD bit can be enabled to cause an interrupt condition on INTB.
Note that when the transmit synchronizer is used, the TSYNCn signal should be set as an output (TSIO = 1) and
the recovered frame-sync pulse will be output on this signal. The recovered CRC-4 multi-frame sync pulse will be
output if enabled with
TIOCR.0 (TSM = 1).
Other key points concerning the E1 transmit synchronizer:
1) The Tx synchronizer is not operational when the transmit elastic store is enabled, including IBO modes.
2) The Tx synchronizer does not perform CRC-6 alignment verification (ESF mode) and does not verify
CRC-4 codewords.
The Tx synchronizer cannot search for the CAS multiframe.
Table 9-16 shows the registers related to the transmit
synchronizer.
Table 9-16. Registers Related to the Transmit Synchronizer
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Transmit Synchronizer Control Register
(
TSYNCC)
18Eh
Resynchronization control for the transmit
synchronizer.
Transmit Control Register 3 (TCR3) 183h
TFM bit selects between D4 and ESF for the
transmit synchronizer.
Transmit Latched Status Register 3
(
TLS3)
192h
Provides latched status for the transmit
synchronizer.
Transmit Interrupt Mask Register 3
(
TIM3)
1A2h Provides mask bits for the TLS3 status.
Transmit I/O Configuration Register
(
TIOCR)
184h TSYNCn should be set as an output.
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex); where n = 2 to 8 for Framers 2 to 8.