Datasheet

DS26518 8-Port T1/E1/J1 Transceiver
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9.2.2 CLKO Output Clock Generation
This clock output is derived from MCLK based upon the setting of the CLKOSEL[2:0] bits in the GTCCR3
register.The reference for the PLL is not the input clock on MCLK, but the scaled version of MCLK (1.544MHz or
2.048MHz). The
LTRCR.T1J1E1S bit also selects the proper PLL for use in generating the appropriate frequency.
This clock output pin is provided as an additional feature to eliminate the need for another board oscillator.
Table 9-1. CLKO Frequency Selection
CLKOSEL[3:0] CLKO (kHz)
0000 2048
0001 4096
0010 8192
0011 16384
0100 1544
0101 3088
0110 6176
0111 12352
1000 1536
1001 3072
1010 6144
1011 12288
1100 32
1101 64
1110 128
1111 256