Datasheet

DS26518 8-Port T1/E1/J1 Transceiver
312 of 312
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17. DOCUMENT REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
022007 New Product Release. —
060607
In the Absolute Maximum Ratings portion of Section 12, added Note 1 stating
that specifications to -40
°C are guaranteed by design (GBD) and not production
tested.
267
080607
Updated data sheet to reflect new features with B1 die revision:
HDLC-256 Controller—introduced in Section 9.10 and described in Section
9.10.3.
Extended BERT Registers—introduced in Section 9.13 and defined in Section
10.6.1.
75, 77, 101, 259
Removed commercial temperature range product option from the Ordering
Information table and Operating Parameters (Section 12).
1
Added content to TCLKn pin description (Section 8.1). 21
Clarified how Read Bar/Data-Strobe Bar and Write Bar/ Read-Write Bar function
in Intel and Motorola bus modes (Section 8.1).
25
Added instruction in Step 5 of the Example Device Initialization and Sequence
(Section 9.4.1) to increase the frequency of the internally generated clock which
is supplied to the framers.
34
Added definition for Receive Master Mode Register bit 5 (RMMR.5) which, when
set, disables the receive-side synchronizer in the framer. This feature is new with
revision B1.
165
103008
Replaced package drawing with table providing link to package drawing (Section
16).
311