Datasheet

DS26518 8-Port T1/E1/J1 Transceiver
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14.3 JTAG ID Codes
Table 14-2. ID Code Structure
DEVICE
REVISION
ID[31:28]
DEVICE CODE
ID[27:12]
MANUFACTURER’S CODE
ID[11:1]
REQUIRED
ID[0]
DS26519 Consult factory 0000000010001011 00010100001 1
DS26518 Consult factory 0000000010001010 00010100001 1
DS26514 Consult factory 0000000010001100 00010100001 1
14.4 Test Registers
IEEE 1149.1 requires a minimum of two test registers: the Bypass Register and the Boundary Scan Register. An
optional test register, the Identification Register, has been included with the DS26518 design. The Identification
Register is used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
14.4.1 Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells,
and is n bits in length.
14.4.2 Bypass Register
This register is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ
instructions, providing a short path between JTDI and JTDO.
14.4.3 Identification Register
The Identification Register contains a 32-bit shift register and a 32-bit latched parallel output. This register is
selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.