Datasheet

DS26518 8-Port T1/E1/J1 Transceiver
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9.9.8 Alarms .................................................................................................................................................. 65
9.9.9 Error Count Registers .......................................................................................................................... 67
9.9.10 DS0 Monitoring Function...................................................................................................................... 69
9.9.11 Transmit Per-Channel Idle Code Generation ...................................................................................... 70
9.9.12 Receive Per-Channel Idle Code Insertion............................................................................................ 70
9.9.13 Per-Channel Loopback ........................................................................................................................ 70
9.9.14 E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only)................................................................... 70
9.9.15 T1 Programmable In-Band Loop Code Generator............................................................................... 71
9.9.16 T1 Programmable In-Band Loop Code Detection................................................................................ 72
9.9.17 Framer Payload Loopbacks ................................................................................................................. 73
9.10 HDLC CONTROLLERS ................................................................................................................74
9.10.1 HDLC-64 Controller.............................................................................................................................. 74
9.10.2 Transmit HDLC-64 Controller .............................................................................................................. 78
9.10.3 HDLC-256 Controller............................................................................................................................ 80
9.11 POWER-SUPPLY DECOUPLING....................................................................................................84
9.12 LINE INTERFACE UNITS (LIUS)....................................................................................................85
9.12.1 LIU Operation....................................................................................................................................... 87
9.12.2 Transmitter ........................................................................................................................................... 88
9.12.3 Receiver ............................................................................................................................................... 91
9.12.4 Hitless Protection Switching (HPS)...................................................................................................... 95
9.12.5 Jitter Attenuator.................................................................................................................................... 96
9.12.6 LIU Loopbacks ..................................................................................................................................... 97
9.13 BIT ERROR-RATE TEST FUNCTION (BERT) ...............................................................................100
9.13.1 BERT Repetitive Pattern Set ............................................................................................................. 101
9.13.2 BERT Error Counter........................................................................................................................... 101
10. DEVICE REGISTERS .....................................................................................................102
10.1 REGISTER LISTINGS .................................................................................................................102
10.1.1 Global Register List............................................................................................................................ 103
10.1.2 Framer Register List........................................................................................................................... 104
10.1.3 LIU Register List................................................................................................................................. 111
10.1.4 BERT Register List............................................................................................................................. 112
10.1.5 HDLC-256 Register List ..................................................................................................................... 113
10.2 REGISTER BIT MAPS ................................................................................................................114
10.2.1 Global Register Bit Map ..................................................................................................................... 114
10.2.2 Framer Register Bit Map .................................................................................................................... 115
10.2.3 LIU Register Bit Map .......................................................................................................................... 125
10.2.4 BERT Register Bit Map...................................................................................................................... 126
10.2.5 HDLC-256 Register Bit Map .............................................................................................................. 127
10.3 GLOBAL REGISTER DEFINITIONS...............................................................................................128
10.4 FRAMER REGISTER DESCRIPTIONS...........................................................................................145
10.4.1 Receive Register Descriptions........................................................................................................... 145
10.4.2 Transmit Register Descriptions.......................................................................................................... 204
10.5 LIU REGISTER DEFINITIONS .....................................................................................................240
10.6 BERT REGISTER DEFINITIONS .................................................................................................250
10.6.1 Extended BERT Register Definitions ................................................................................................. 258
10.7 HDLC-256 REGISTER DEFINITIONS ..........................................................................................262
10.7.1 Transmit HDLC-256 Register Definitions........................................................................................... 262
10.7.2 Receive HDLC-256 Register Definitions............................................................................................ 267
11. FUNCTIONAL TIMING ...................................................................................................272
11.1 T1 RECEIVER FUNCTIONAL TIMING DIAGRAMS ..........................................................................272
11.2 T1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS ....................................................................277
11.3 E1 RECEIVER FUNCTIONAL TIMING DIAGRAMS ..........................................................................282
11.4 E1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS ....................................................................286
12. OPERATING PARAMETERS.........................................................................................291