Datasheet

DS26518 8-Port T1/E1/J1 Transceiver
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Register Name:
RH256FDR1
Register Description:
Receive HDLC-256 FIFO Data Register 1
Register Address:
151Ch + (20h x (n - 1)) : where n = 1 to 8
Bit # 7 6 5 4 3 2 1 0
Name
— — — —
RPS2 RPS1 RPS0 RFDV
Default 0 0 0 0 X X X 0
Note: The FIFO data and status are updated when the receive FIFO data (RH256FDR2.RFD[7:0]) is read. Reading this register
reflects the status of the next read of RH256FDR2.
Bits 3 to 1: Receive Packet Status (RPS[2:0]). These three bits indicate the status of the received packet and
packet data.
000 = packet middle
001 = packet start
010 = reserved
011 = reserved
100 = packet end: good packet
101 = packet end: FCS errored packet
110 = packet end: invalid packet (a noninteger number of bytes)
111 = packet end: aborted packet
Bit 0: Receive FIFO Data Valid (RFDV). When 0, the receive FIFO data (RFD[7:0]) is invalid (the receive FIFO is
empty). When 1, the receive FIFO data (RFD[7:0]) is valid.
Register Name:
RH256FDR2
Register Description:
Receive HDLC-256 FIFO Data Register 2
Register Address:
151Dh + (20h x (n - 1)) : where n = 1 to 8
Bit # 7 6 5 4 3 2 1 0
Name RFD7 RFD6 RFD5 RFD4 RFD3 RFD2 RFD1 RFD0
Default X X X X X X X X
Note: Reading this register when RH256FDR1.RFDV = 0 can result in a loss of data.
Bits 7 to 0: Receive FIFO Data (RFD[7:0]). These eight bits are the packet data stored in the receive FIFO.
RFD[7] is the MSB, and RFD[0] is the LSB. If bit reordering is disabled, RFD[0] is the first bit received, and RFD[7]
is the last bit received. If bit reordering is enabled, RFD[7] is the first bit received, and RFD[0] is the last bit
received.