Datasheet

DS26518 8-Port T1/E1/J1 Transceiver
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Register Name:
RH256SR
Register Description:
Receive HDLC-256 Status Register
Register Address:
1514h+ (20h x (n - 1)) : where n = 1 to 8
Bit # 7 6 5 4 3 2 1 0
Name
— — — — —
RFF RFE RHDA
Default 0 0 0 0 0 0 0 0
Bit 2: Receive FIFO Full (RFF). When 0, the receive FIFO contains 255 or less bytes of data. When 1, the receive
FIFO is full.
Bit 1: Receive FIFO Empty (RFE). When 0, the receive FIFO contains at least one byte of data. When 1, the
receive FIFO is empty.
Bit 0: Receive HDLC-256 Data Available (RHDA). When 0, the receive FIFO contains less data than the receive
HDLC-256 data available level (RDAL[4:0]). When 1, the receive FIFO contains the same or more data than the
receive HDLC-145 data available level.
Register Name:
RH256SRL
Register Description:
Receive HDLC-256 Status Register Latched
Register Address:
1516h + (20h x (n - 1)) : where n = 1 to 8
Bit # 7 6 5 4 3 2 1 0
Name RFOL —
—
RPEL RPSL RFFL
—
RHDAL
Default 0 0 0 0 0 0 0 0
Bit 7: Receive FIFO Overflow Latched (RFOL). This bit is set when a receive FIFO overflow condition occurs. An
overflow condition results in a loss of data.
Bit 4: Receive Packet End Latched (RPEL). This bit is set when an end of packet is stored in the receive FIFO.
Bit 3: Receive Packet Start Latched (RPSL). This bit is set when a start of packet is stored in the receive FIFO.
Bit 2: Receive FIFO Full Latched (RFFL). This bit is set when the RFF bit transitions from 0 to 1.
Bit 0: Receive HDLC-256 Data Available Latched (RHDAL). This bit is set when the RHDA bit transitions from
0 to 1.