Datasheet

DS26518 8-Port T1/E1/J1 Transceiver
266 of 312
Register Name:
TH256SRL
Register Description:
Transmit HDLC-256 Status Register Latched
Register Address:
1506h + (20h x (n - 1)) : where n = 1 to 8
Bit # 7 6 5 4 3 2 1 0
Name — — TFOL TFUL TPEL — TFEL THDAL
Default 0 0 0 0 0 0 0 0
Bit 5: Transmit FIFO Overflow Latched (TFOL). This bit is set when a transmit FIFO overflow condition occurs.
Bit 4: Transmit FIFO Underflow Latched (TFUL). This bit is set when a transmit FIFO underflow condition
occurs. An underflow condition results in a loss of data.
Bit 3: Transmit Packet End Latched (TPEL). This bit is set when an end of packet is read from the transmit FIFO.
Bit 1: Transmit FIFO Empty Latched (TFEL). This bit is set when the TFE bit transitions from 0 to 1. Note: This
bit is also set when TH256CR1.TFRST is deasserted.
Bit 0: Transmit HDLC-256 Data Available Latched (THDAL). This bit is set when the THDA bit transitions from 0
to 1. Note: This bit is also set when TH256CR1.TFRST is deasserted.
Register Name:
TH256SRIE
Register Description:
Transmit HDLC-256 Status Register Interrupt Enable
Register Address:
1508h + (20h x (n-1)) : where n = 1 to 8
Bit # 7 6 5 4 3 2 1 0
Name — — TFOIE TFUIE TPEIE — TFEIE THDAIE
Default 0 0 0 0 0 0 0 0
Bit 5: Transmit FIFO Overflow Interrupt Enable (TFOIE). This bit enables an interrupt if the TFOL bit is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 4: Transmit FIFO Underflow Interrupt Enable (TFUIE). This bit enables an interrupt if the TFUL bit is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 3: Transmit Packet End Interrupt Enable (TPEIE). This bit enables an interrupt if the TPEL bit is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 1: Transmit FIFO Empty Interrupt Enable (TFEIE). This bit enables an interrupt if the TFEL bit is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 0: Transmit HDLC-256 Data Available Interrupt Enable (THDAIE). This bit enables an interrupt if the THDAL
bit is set.
0 = interrupt disabled
1 = interrupt enabled