Datasheet

DS26518 8-Port T1/E1/J1 Transceiver
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Register Name:
TH256FDR1
Register Description:
Transmit HDLC-256 FIFO Data Register 1
Register Address:
1502h + (20h x (n - 1)) : where n = 1 to 8
Bit # 7 6 5 4 3 2 1 0
Name
— — — — — — —
TDPE
Default 0 0 0 0 0 0 0 0
Bit 0: Transmit FIFO Data Packet End (TDPE). When 0, the transmit FIFO data is not a packet end. When 1, the
transmit FIFO data is a packet end. This bit should be written before the last byte of the packet is written into
TH256FDR2.
Register Name:
TH256FDR2
Register Description:
Transmit HDLC-256 FIFO Data Register 2
Register Address:
1503h + (20h x (n - 1)) : where n = 1 to 8
Bit # 7 6 5 4 3 2 1 0
Name TFD7 TFD6 TFD5 TFD4 TFD3 TFD2 TFD1 TFD0
Default 0 0 0 0 0 0 0 0
Note: When read, the value of these bits is always zero.
Bits 7 to 0: Transmit FIFO Data (TFD[7:0]). These eight bits are the packet data to be stored in the transmit
FIFO. TFD[7] is the MSB, and TFD[0] is the LSB. If bit reordering is disabled, TFD[0] is the first bit transmitted, and
TFD[7] is the last bit transmitted. If bit reordering is enabled, TFD[7] is the first bit transmitted, and TFD[0] is the
last bit transmitted.