Datasheet

DS26518 8-Port T1/E1/J1 Transceiver
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Register Name:
BLSR2
Register Description:
BERT Latched Status Register 2
Register Address:
1404h + (10h x (n - 1)) : where n = 1 to 8
Bit # 7 6 5 4 3 2 1 0
Name — — — — — BED BBCO BECO
Default 0 0 0 0 0 0 0 0
Note: All latched bits in this register can create interrupts.
Bit 2: BERT Bit Error Detected Event (BED). A latched bit that is set when a bit error is detected. The receive
BERT must be in synchronization for it to detect bit errors.
Bit 1: BERT Bit Counter Overflow Event (BBCO). A latched bit that is set when the 32-bit BERT bit counter
(BBC) overflows.
Bit 0: BERT Error Counter Overflow Event (BECO). A latched bit that is set when the 24-bit BERT error counter
(BEC) overflows.
Register Name:
BSIM2
Register Description:
BERT Status Interrupt Mask Register 2
Register Address:
1405h + (10h x (n - 1)) : where n = 1 to 8
Bit # 7 6 5 4 3 2 1 0
Name — — — — — BED BBCO BECO
Default 0 0 0 0 0 0 0 0
Bit 2: Bit Error Detected Event (BED)
0 = interrupt masked
1 = interrupt enabled
Bit 1: BERT Bit Counter Overflow Event (BBCO)
0 = interrupt masked
1 = interrupt enabled
Bit 0: BERT Error Counter Overflow Event (BECO)
0 = interrupt masked
1 = interrupt enabled