Datasheet

DS26518 8-Port T1/E1/J1 Transceiver
26 of 312
NAME PIN TYPE FUNCTION
WRB/
RWB
R7 Input
Write Bar/Read-Write Bar. This active-low signal along with CSB qualifies write
access to one of the DS26518 registers. Data at D[7:0] is written into the
addressed register, in Intel bus mode, at the rising edge of WRB while CSB is low
or, in Motorola bus mode, at the rising edge of DSB while RWB and CSB are low.
INTB
R9
Output,
Tri-
Stateable
Interrupt Bar. This active-low output is asserted when an unmasked interrupt
event is detected. INTB will be deasserted (and tri-stated) when all interrupts
have been acknowledged and serviced. Extensive mask bits are provided at the
global level, framer, LIU, and BERT level.
SPI_SEL/
AL/RSIGF/FLOS1
C3
Input with
internal
pulldown/
Output
SPI Serial Bus Mode Select/Analog Loss/Receive Signaling Freeze/Framer
LOS
SPI_SEL: 0 = Parallel Bus Mode, 1 = SPI Serial Bus Mode
AL/RSIGF/FLOS1: Analog LOS reflects the loss of signal detected by the LIU
front-end; framer LOS is LOS detection by the corresponding framer. The same
pins can reflect receive-signaling freeze indications. This selection can be made
by settings in Global Transceiver Control Register (
GTCR1). AL/RSIGF/FLOS1
are available by setting the
GTCR1.528MD bit to 1.
BTS M13 Input
Bus Type Select. Set high to select Motorola bus timing, low to select Intel bus
timing. This pin controls the function of the RDB/DSB and WRB pins. Note: If SPI
mode is selected by the SPI_SEL pin, this pin must be tied low.
SYSTEM INTERFACE
MCLK B7 Input
Master Clock. This is an independent free-running clock whose input can be a
multiple of 2.048MHz ±50ppm or 1.544MHz ±50ppm. The clock selection is
available by bits MPS0 and MPS1 and FREQSEL. Multiple of 2.048MHz can be
internally adapted to 1.544MHz. Multiple of 1.544MHz can be adapted to
2.048MHz. Note that TCLKn must be 2.048MHz for E1 and 1.544MHz for T1/J1
operation. See
Table 10-14.
RESETB
J12 Input
Reset Bar. Active-low reset. This input forces the complete DS26518 reset. This
includes reset of the registers, framers, and LIUs.
REFCLKIO A7
Input/
Output
Reference Clock Input/Output
Input: A 2.048MHz or 1.544MHz clock input. This clock can be used to generate
the backplane clock. This allows for the users to synchronize the system
backplane with the reference clock. The other options for the backplane clock
reference are LIU-received clocks or MCLK.
Output: This signal can also be used to output a 1.544MHz or 2.048MHz
reference clock. This allows for multiple DS26518s to share the same reference
for generation of the backplane clock. Hence, in a system consisting of multiple
DS26518s, one can be a master and others a slave using the same reference
clock.
TEST
DIGIOEN D8
Input,
Pullup
Digital Enable. When this pin and JTRST are pulled low, all digital I/O pins are
placed in a high-impedance state. If this pin is high the digital I/O pins operate
normally. This pin must be connected to V
DD
for normal operation.
JTRST
L5
Input,
Pullup
JTAG Reset. JTRST is used to asynchronously reset the test access port
controller. After power-up, JTRST must be toggled from low to high. This action
sets the device into the JTAG DEVICE ID mode. Pulling JTRST low restores
normal device operation. JTRST is pulled high internally via a 10kΩ resistor
operation. If boundary scan is not used, this pin should be held low.
JTMS K4
Input,
Pullup
JTAG Mode Select. This pin is sampled on the rising edge of JTCLK and is used
to place the test access port into the various defined IEEE 1149.1 states. This pin
has a 10kΩ pullup resistor.
JTCLK F5 Input
JTAG Clock. This signal is used to shift data into JTDI on the rising edge and out
of JTDO on the falling edge.
JTDI H4
Input,
Pullup
JTAG Data In. Test instructions and data are clocked into this pin on the rising
edge of JTCLK. This pin has a 10kΩ pullup resistor.
JTDO J4
Output,
High
Impedance
JTAG Data Out. Test instructions and data are clocked out of this pin on the
falling edge of JTCLK. If not used, this pin should be left unconnected.