Datasheet

DS26518 8-Port T1/E1/J1 Transceiver
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Register Name:
BLSR1
Register Description:
BERT Latched Status Register 1
Register Address:
1402h + (10h x (n - 1)) : where n = 1 to 8
Bit # 7 6 5 4 3 2 1 0
Name BRA1C BRA0C BRLOSC BSYNCC BRA1D BRA0D BRLOSD BSYNCD
Default 0 0 0 0 0 0 0 0
Note: All latched bits in this register can create interrupts.
Bit 7: BERT Receive All-Ones Condition Clear (BRA1C). A latched bit that is set when the BERT transitions out
of all-ones condition.
Bit 6: BERT Receive All-Zeros Condition Clear (BRA0C). A latched bit that is set when the BERT transitions out
of all-zeros condition.
Bit 5: BERT Receive Loss of Synchronization Condition Clear (BRLOSC). A latched bit that is set when the
BERT transitions out of loss of synchronization condition.
Bit 4: BERT in Synchronization Condition Clear (BSYNCC). A latched bit that is set when the BERT transitions
out of synchronization condition.
Bit 3: BERT Receive All-Ones Condition Detect (BRA1D). A latched bit that is set when 32 consecutive ones
are received.
Bit 2: BERT Receive All-Zeros Condition Detect (BRA0D). A latched bit that is set when 32 consecutive zeros
are received.
Bit 1: BERT Receive Loss of Synchronization Condition Detect (BRLOSD). A latched bit that is set whenever
the receive BERT begins searching for a pattern.
Bit 0: BERT in Synchronization Condition Detect (BSYNCD). A latched bit that is set when the incoming pattern
matches for 32 consecutive bit positions.