Datasheet

DS26518 8-Port T1/E1/J1 Transceiver
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10.6.1 Extended BERT Register Definitions
Table 10-28. Extended BERT Register Set
ADDRESS NAME DESCRIPTION
R/W
1400h BC3 BERT Control Register 3
R/W
1401h BRSR BERT Real-Time Status Register
R
1402h BLSR1 BERT Latched Status Register 1
R/W
1403h BSIM1 BERT Status Interrupt Mask Register 1
R/W
1404h BLSR2 BERT Latched Status Register 2
R/W
1405h BSIM2 BERT Status Interrupt Mask Register 2
R/W
Register Name:
BC3
Register Description:
BERT Control Register 3
Register Address:
1400h + (10h x (n - 1)) : where n = 1 to 8
Bit # 7 6 5 4 3 2 1 0
Name — — — — — — 55OCT BALIGN
Default 0 0 0 0 0 0 0 0
Bit 1: 55 Octet Pattern (55OCT). This bit selects data pattern used by the transmit and receive circuits.
0 = 55 Octet pattern disabled.
1 = 55 Octet pattern enabled, when modified 55 Octet (Daly) pattern is selected by
BC1.PSn register bits.
Bit 0: Byte Alignment to DS0 Boundary (BALIGN). A low-to-high transition causes the transmit BERT pattern to
be byte-aligned to the DS0 boundary. This bit should be toggled from low to high when a pattern load is executed
(
BC1.TC).
Register Name:
BRSR
Register Description:
BERT Real-Time Status Register
Register Address:
1401h + (10h x (n - 1)) : where n = 1 to 8
Bit # 7 6 5 4 3 2 1 0
Name — — — — BRA1 BRA0 BRLOS BSYNC
Default 0 0 0 0 0 0 0 0
Bit 3: BERT Receive All-Ones Condition (BRA1). This bit is set when 32 consecutive ones are received and
clears when at least one “zero” is received.
Bit 2: BERT Receive All-Zeros Condition (BRA0). This bit is set when 32 consecutive zeros are received and
clears when at least one “one” is received.
Bit 1: BERT Receive Loss of Synchronization Condition (BRLOS). This bit is set whenever the receive BERT
begins searching for a pattern and clears when BERT enters SYNC condition.
Bit 0: BERT in Synchronization Condition (BSYNC). This bit is set when the incoming pattern matches for 32
consecutive bit positions and remains set until the BERT enters loss of synchronization condition.