Datasheet

DS26518 8-Port T1/E1/J1 Transceiver

246 of 312

LLSR

LIU Latched Status Register

1005h + (20h x (n - 1)) : where n = 1 to 8

Bit # 7 6 5 4 3 2 1 0

Name JALTC OCC SCC LOSC JALTS OCD SCD LOSD

Default 0 0 0 0 0 0 0 0

Note: All bits in this register are latched and can create interrupts.

Bit 7: Jitter Attenuator Limit Trip Clear (JALTC). This latched bit is set when a JA limit trip condition was

detected and then removed.

Bit 6: Open-Circuit Clear (OCC).

This latched bit is set when an open circuit condition was detected at TTIPn and

TRINGn and then removed.

Bit 5: Short-Circuit Clear (SCC). This latched bit is set when a short circuit condition was detected at TTIPn and

TRINGn and then removed.

Bit 4: Loss of Signal Clear (LOSC). This latched bit is set when a loss of signal condition was detected at RTIPn

and RRINGn and then removed.

Bit 3: Jitter Attenuator Limit Trip Set (JALTS). This latched bit is set when the jitter attenuator trip condition is

detected.

Bit 2: Open-Circuit Detect (OCD).

This latched bit is set when open-circuit condition is detected at TTIPn and

TRINGn. This bit is not functional in T1 CSU operating modes (T1 LBO 5, LBO 6, and LBO 7).

Bit 1: Short-Circuit Detect (SCD). This latched bit is set when short-circuit condition is detected at TTIPn and

TRINGn. This bit is not functional in T1 CSU operating modes (T1 LBO 5, LBO 6, and LBO 7).

Bit 0: Loss of Signal Detect (LOSD).

This latched bit is set when an LOS condition is detected at RTIPn and

RRINGn.