Datasheet

DS26518 8-Port T1/E1/J1 Transceiver
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Register Name:
LTRCR
Register Description:
LIU Transmit Receive Control Register
Register Addresses:
1000h + (20h x (n - 1)) : where n = 1 to 8
Bit # 7 6 5 4 3 2 1 0
Name — RHPM JADS1 JADS0 JAPS1 JAPS0 T1J1E1S LSC
Default 0 0 0 0 0 0 0 0
Bit 6: Receive Hitless Protection Mode (RHPM)
0 = Normal operation using software for hitless protection (RIMPON).
1 = Hitless protection switching mode using TXENABLE pin.
If the TXENABLE pin is low and this bit is set to one, the receive LIU will present a high impedance to the line,
overriding the receive impedance selection register bits
LRISMR.RIMPM[2:0].
Bits 5 and 4 : Jitter Attenuator Depth Select (JADS[1:0])
JADS1 JADS0 FUNCTION
0 0 Jitter attenuator FIFO depth 128 bits.
0 1 Jitter attenuator FIFO depth 64 bits.
1 0 Jitter attenuator FIFO depth 32 bits.
1 1 Jitter attenuator FIFO depth 16 bits (used for delay-sensitive applications).
Bits 3 and 2: Jitter Attenuator Position Select (JAPS[1:0]). These bits are used to select the position of the jitter
attenuator.
JAPS1 JAPS0 FUNCTION
0 0 Jitter attenuator in the receive path.
0 1 Jitter attenuator in the transmit path.
1 0 Jitter attenuator disabled.
1 1 Jitter attenuator disabled.
Bit 1: T1J1E1 Selection (T1J1E1S). This bit configures the LIU for E1 or T1/J1 operation.
0 = E1
1 = T1 or J1
Bit 0: LOS Selection Criteria (LSC). This bit is used for LIU LOS selection criteria.
E1 Mode
0 = G.775
1 = ETS 300 233
T1/J1 Mode
0 = T1.231
1 = T1.231