Datasheet
DS26518 8-Port T1/E1/J1 Transceiver
24 of 312
NAME PIN TYPE FUNCTION
RMSYNC1/
RFSYNC1
C4
RMSYNC2/
RFSYNC2
C6
RMSYNC3/
RFSYNC3
P4
RMSYNC4/
RFSYNC4
P6
RMSYNC5/
RFSYNC5
P10
RMSYNC6/
RFSYNC6
N12
RMSYNC7/
RFSYNC7
D11
RMSYNC8/
RFSYNC8
E12
Output
Receive Multiframe/Frame Synchronization 1 to 8. A dual function pin to
indicate frame or multiframe synchronization. RFSYNCn is an extracted 8kHz
pulse, one RCLKn wide that identifies frame boundaries. RMSYNCn is an
extracted pulse, one RCLKn wide (elastic store disabled) or one RSYSCLKn wide
(elastic store enabled), that identifies multiframe boundaries. When the receive
elastic store is enabled, the RMSYNCn signal indicates the multiframe sync on
the system (backplane) side of the elastic store. In E1 mode, this pin can indicate
either the CRC-4 or CAS multiframe as determined by the RSMS2 control bit in
the Receive I/O Configuration register (
RIOCR.1).
RSIG1 D4
RSIG2 E6
RSIG3 M5
RSIG4 R5
RSIG5 R11
RSIG6 R13
RSIG7 A12
RSIG8 F12
Output
Receive Signaling 1 to 8. Outputs signaling bits in a PCM format. Updated on
rising edges of RCLKn when the receive-side elastic store is disabled. Updated
on the rising edges of RSYSCLKn when the receive-side elastic store is enabled.
See
Table 9-7.
RCHBLK1/
RCHCLK1
E4
RCHBLK2/
RCHCLK2
B5
RCHBLK3/
RCHCLK3
L6
RCHBLK4/
RCHCLK4
T5
RCHBLK5/
RCHCLK5
T11
RCHBLK6/
RCHCLK6
T13
RCHBLK7/
RCHCLK7
C12
RCHBLK8/
RCHCLK8
G13
Output
Receive Channel Block/Receive Channel Block Clock. This pin can be
configured to output either RCHBLK or RCHCLK.
RCHBLK[1:8]. RCHBLKn is a user-programmable output that can be forced high
or low during any of the 24 T1 or 32 E1 channels. It is synchronous with RCLKn
when the receive-side elastic store is disabled. It is synchronous with RSYSCLKn
when the receive-side elastic store is enabled. This pin is useful for blocking
clocks to a serial UART or LAPD controller in applications where not all channels
are used such as fractional service, 384kbps service, 768kbps, or ISDN-PRI. Also
useful for locating individual channels in drop-and-insert applications, for external
per-channel loopback, and for per-channel conditioning.
RCHCLK[1:8]. RCHCLKn is a 192kHz (T1) or 256kHz (E1) clock that pulses high
during the LSB of each channel. It is synchronous with RCLKn when the receive-
side elastic store is disabled. It is synchronous with RSYSCLKn when the
receive-side elastic store is enabled. It is useful for parallel-to-serial conversion of
channel data.
BPCLK1 E8 Output
Backplane Clock 1. Programmable clock output that can be set to 2.048MHz,
4.096MHz, 8.192MHz, or 16.384MHz. The reference for this clock can be
RCLK[8:1], a 1.544MHz or 2.048MHz clock frequency derived from MCLK, or an
external reference clock (REFCLKIO). This allows system clocks to be referenced
from external sources, the T1J1E1 recovered clocks, or the MCLK oscillator.
CLKO/
RLF/LTC1
D3 Output
Clock Out. Clock output pin that can be programmed to output numerous
frequencies referenced to MCLK. Frequencies available: 1.544MHz, 2.048MHz,
4.096MHz, 8.192MHz, 12.288MHz, 16.384MHz, 256kHz, and 64kHz.
GTCCR3.CLKOSEL[2:0] selects the frequency.
Receive Loss of Frame/Loss of Transmit Clock. This pin can also be
programmed to either toggle high when the synchronizer is searching for the
frame and multiframe, or to toggle high if the TCLKn pin has not been toggled for
approximately three clock periods.
RLF/LTC1 is available on the DS26518 when
GTCR1.528MD = 1.