Datasheet

DS26518 8-Port T1/E1/J1 Transceiver
23 of 312
NAME PIN TYPE FUNCTION
RECEIVE FRAMER
RSER1 E5
RSER2 D6
RSER3 N4
RSER4 N6
RSER5 M11
RSER6 M12
RSER7 B12
RSER8 F11
Output
Received Serial Data 1 to 8. Received NRZ serial data. Updated on rising edges
of RCLKn when the receive-side elastic store is disabled. Updated on the rising
edges of RSYSCLKn when the receive-side elastic store is enabled.
When IBO mode is used, the RSERn pins can output data for multiple framers.
The RSERn data is synchronous to RSYSCLKn. See Section
9.8.2 and Table
9-6
.
RCLK1 F4
RCLK2 G4
RCLK3 L4
RCLK4 M4
RCLK5 K13
RCLK6 J13
RCLK7 F13
RCLK8 E13
Output
Receive Clock 1 to 8. A 1.544MHz (T1) or 2.048MHz (E1) clock that is used to
clock data through the receive-side framer. This clock is recovered from the
signal at RTIPn and RRINGn. RSERn data is output on the rising edge of RCLKn.
RCLKn is used to output RSERn when the elastic store is not enabled or IBO is
not used. When the elastic store is enabled or IBO is used, the RSERn is clocked
by RSYSCLKn.
RSYSCLK1 L12 Input
Receive System Clock 1. 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or
16.384MHz receive backplane clock. Only used when the receive-side elastic
store function is enabled. Should be tied low in applications that do not use the
receive-side elastic store. Multiple of 2.048MHz is expected when the IBO mode
is used. Note: If the
GTCR1.528MD bit is set, RSYSCLK1 becomes the master
RSYSCLK for all framers.
RSYSCLK2/
RLF/LTC2
E3
RSYSCLK3/
RLF/LTC3
M3
RSYSCLK4/
RLF/LTC4
N3
RSYSCLK5/
RLF/LTC5
N14
RSYSCLK6/
RLF/LTC6
M14
RSYSCLK7/
RLF/LTC7
E14
RSYSCLK8/
RLF/LTC8
D14
Input with
internal
pulldown/
Output
Receive System Clock 2 to 8. 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or
16.384MHz receive backplane clock. Only used when the receive-side elastic
store function is enabled. Should be tied low in applications that do not use the
receive-side elastic store. Multiple of 2.048MHz is expected when the IBO Mode
is used.
Receive Loss of Frame/Loss of Transmit Clock. This pin can also be
programmed to either toggle high when the synchronizer is searching for the
frame and multiframe or to toggle high if the TCLKn pin has not been toggled for
approximately three clock periods.
RLF/LTC[8:2] are available when
GTCR1.528MD = 1.
Note: If the GTCR1.528MD bit is set, RSYSCLK1 becomes the master
RSYSCLK for all framers.
RSYNC1 A4
RSYNC2 B6
RSYNC2 N5
RSYNC2 T6
RSYNC5 R10
RSYNC6 P12
RSYNC7 C11
RSYNC8 D13
Input/
Output
Receive Synchronization 1 to 8. If the receive-side elastic store is enabled, this
signal is used to input a frame or multiframe boundary pulse. If set to output
frame boundaries, RSYNCn can be programmed to output double-wide pulses on
signaling frames in T1 mode. In E1 mode, RSYNCn out can be used to indicate
CAS and CRC-4 multiframe. The DS26518 can accept an H.100-compatible
synchronization signal. The default direction of this pin at power-up is input, as
determined by the RSIO control bit in the
RIOCR.2 register.