Datasheet

DS26518 8-Port T1/E1/J1 Transceiver

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RLS3 (E1 Mode)

Receive Latched Status Register 3

092h + (200h x (n - 1)) : where n = 1 to 8

Bit # 7 6 5 4 3 2 1 0

Name LORCC — V52LNKC RDMAC LORCD — V52LNKD RDMAD

Default 0 0 0 0 0 0 0 0

Note: All bits in this register are latched and can create interrupts. See RLS3 for T1 Mode.

Bit 7: Loss of Receive Clock Clear (LORCC). Change of state indication. Set when an LORC condition has

cleared (falling edge detect of LORC).

Bit 5: V5.2 Link Detected Clear (V52LNKC). Change of state indication. Set when a V52LNK condition has

cleared (falling edge detect of V52LNK).

Bit 4: Receive Distant MF Alarm Clear (RDMAC). Change of state indication. Set when an RDMA condition has

cleared (falling edge detect of RDMA).

Bit 3: Loss of Receive Clock Detect (LORCD). Change of state indication. Set when the RCLKn pin has not

transitioned for one channel time (rising edge detect of LORC).

Bit 1: V5.2 Link Detect (V52LNKD). Change of state indication. Set on detection of a V5.2 link identification signal.

(G.965). This is the rising edge detect of V52LNK.

Bit 0: Receive Distant MF Alarm Detect (RDMAD). Change of state indication. Set when bit 6 of time slot 16 in

frame 0 has been set for two consecutive multiframes. This alarm is not disabled in the CCS signaling mode. This

is the rising edge detect of RDMA.