Datasheet

DS26518 8-Port T1/E1/J1 Transceiver
169 of 312
Register Name:
RCR3
Register Description:
Receive Control Register 3
Register Address:
083h + (200h x (n - 1)) : where n = 1 to 8
Bit # 7 6 5 4 3 2 1 0
Name — uALAW RSERC BINV1 BINV0 — PLB FLB
Default 0 0 0 0 0 0 0 0
Bit 6: u-Law or A-Law Digital Milliwatt Code Select (uALAW)
0 = u-law code is inserted based on
T1RDMWE1–3 or E1RDMWE1–4 registers.
1 = A-law code is inserted based on
T1RDMWE1–3 or E1RDMWE1–4 registers.
Bit 5: RSERn Control (RSERC)
0 = Allow RSERn to output data as received under all conditions (normal operation).
1 = Force RSERn to one under loss of frame alignment conditions.
Bits 4 and 3: Receive Bit Inversion (BINV[1:0])
00 = No inversion.
01 = Invert framing.
10 = Invert signaling.
11 = Invert payload.
Bit 1: Payload Loopback (PLB)
0 = Loopback disabled.
1 = Loopback enabled.
When PLB is enabled, the following will occur:
1) Data will be transmitted on TTIPn and TRINGn synchronous with RCLKn instead of TCLKn.
2) All the receive-side signals will continue to operate normally.
3) The TCHCLKn and TCHBLKn signals are forced low.
4) Data at the TSERn, TDATAn, and TSIGn pins is ignored.
In a PLB situation, the DS26518 will loop the 192 bits (248 for E1) of payload data (with BPVs corrected) from the
receive section back to the transmit section. The transmitter will follow the frame alignment provided by the
receiver. The receive frame boundary is automatically fed into the transmit section, such that the transmit frame
position is locked to the receiver (i.e., TSYNCn is sourced from RSYNCn). The FPS framing pattern, CRC-6
calculation, and the FDL bits (FAS word, Si, Sa, E bits, and CRC-4 for E1) are not looped back, they are reinserted
by the DS26518 (i.e., the transmit section will modify the payload as if it was input at TSERn).
Bit 0: Framer Loopback (FLB)
0 = loopback disabled
1 = loopback enabled
This loopback is useful in testing and debugging applications. In FLB, the DS26518 will loop data from the transmit
side back to the receive side. When FLB is enabled, the following will occur:
1) (T1 mode) an unframed all-ones code will be transmitted at TTIPn and TRINGn.
(E1 mode) normal data will be transmitted at TTIPn and TRINGn.
2) Data at RTIPn and RRINGn will be ignored.
3) All receive-side signals will take on timing synchronous with TCLKn instead of RCLKn.
Note that it is not acceptable to have RCLKn tied to TCLKn during this loopback because this will cause an
unstable condition.