Datasheet

DS26518 8-Port T1/E1/J1 Transceiver
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10.4 Framer Register Descriptions
10.4.1 Receive Register Descriptions
See Table 10-3 for the complete framer register list.
Register Name:
RHC
Register Description:
Receive HDLC-64 Control Register
Register Address:
010h + (200h x (n - 1)) : where n = 1 to 8
Bit # 7 6 5 4 3 2 1 0
Name RCRCD RHR RHMS RHCS4 RHCS3 RHCS2 RHCS1 RHCS0
Default 0 0 0 0 0 0 0 0
Bit 7: Receive CRC-16 Display (RCRCD)
0 = Do not write received CRC-16 code to FIFO (default).
1 = Write received CRC-16 code to FIFO after last octet of packet.
Bit 6: Receive HDLC-64 Reset (RHR). Will reset the receive HDLC-64 controller and flush the receive FIFO. Note
that this bit is a acknowledged reset. The host should set this bit and the DS26518 will clear it once the reset
operation is complete. The DS26518 will complete the HDLC-64 reset within 2 frames.
0 = Normal operation.
1 = Reset receive HDLC-64 controller and flush the receive FIFO.
Bit 5: Receive HDLC-64 Mapping Select (RHMS)
0 = Receive HDLC-64 assigned to channels.
1 = Receive HDLC-64 assigned to FDL (T1 mode), Sa bits (E1 mode).
Bits 4 to 0: Receive HDLC-64 Channel Select 4 to 0 (RHCS[4:0]). These bits determine which DS0 is mapped to
the HDLC-64 controller when enabled with RHMS = 0. RHCS[4:0] = all 0s selects channel 1, RHCS[4:0] = all 1s
selects channel 32 (E1). A change to the receive HDLC-64 channel select is acknowledged only after a receive
HDLC-64 reset (RHR).