Datasheet

DS26518 8-Port T1/E1/J1 Transceiver
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Register Name:
GSRR1
Register Description:
Global Software Reset Register 1
Register Address:
00F6h
Bit # 7 6 5 4 3 2 1 0
Name
— — — — H256RST
LRST BRST FRST
Default 0 0 0 0 0 0 0 0
Bit 3: HDLC-256 Software Reset (H256RST). HDLC-256 Channels 1–8 logic and registers are reset with a 0-to-1
transition in this bit. The reset is released when a zero is written to this bit.
0 = Normal operation.
1 = Reset HDLC-256 channels 1–8.
Note: HDLC-64 circuits are reset by the framer software reset.
Bit 2: LIU Software Reset (LRST). LIU Channels 1–8 logic and registers are reset with a 0-to-1 transition in this
bit. The reset is released when a zero is written to this bit.
0 = Normal operation.
1 = Reset LIU channels 1–8.
Bit 1: BERT Software Reset (BRST). BERT Channels 1–8 logic and registers are reset with a 0-to-1 transition in
this bit. The reset is released when a zero is written to this bit.
0 = Normal operation.
1 = Reset BERT channels 1–8.
Bit 0: Framer Software Reset (FRST). Framers 1-8 to logic and registers are reset with a 0-to-1 transition in this
bit. The reset is released when a zero is written to this bit.
0 = Normal operation.
1 = Reset framers 1–8.