Datasheet

DS26518 8-Port T1/E1/J1 Transceiver
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Register Name
GTCR1
Register Description:
Global Transceiver Control Register 1
Register Address:
00F0h
Bit # 7 6 5 4 3 2 1 0
Name GPSEL3 GPSEL2 GPSEL1 — 528MD GIBO GCLE GIPI
Default 0 0 0 0 0 0 0 0
Bits 7 to 5: General-Purpose I/O Pins Select (GPSEL[3:1])
Table 10-13. Output Status Control
GPSEL[3:1] RLF/LTC[8:1] AL/RSIGF/FLOS[8:1]
000 RLF AL
001 LTC AL
010 RLF RSIGF
011 LTC RSIGF
100 RLF FLOS
101 LTC FLOS
110 Reserved Reserved
111 Reserved Reserved
Bit 3: DS26528 Mode (528MD)
0 = Normal operation.
1 = Pin definitions switch to DS26528 pins to obtain pin compatibility with the DS26528.
Normal Operation 528MD
RSYSCLK[8:2] RLF/LTC[8:2]
RSYSCLK1 RSYSCLK1
CLKO RLF/LTC1
TSYSCLK[8:2] AL/RSIGF/FLOS[8:2]
TSYSCLK1 TSYSCLK1
SPI_SEL AL/RSIGF/FLOS1
TSYNC/TSSYNCIO[8:1] TSYNC[8:1]
(Tie low—unused) TSSYNCIO
Bit 2: Ganged IBO Enable (GIBO). This bit is used to select either the internal mux for IBO operation or an
external “wire-OR” operation. Normally this bit should be set = 0 and the internal mux used.
0 = Use internal IBO mux.
1 = Externally “wire-OR” TSERn and RSERn for IBO operation.
Note: Setting GIBO disables the internal IBO mux.
GFCR1 must be set to inform the framers of the IBO
configuration.
Bit 1: Global Counter Latch Enable (GCLE). A low-to-high transition on this bit will, when enabled, latch the
framer performance monitor counters. Each framer can be independently enabled to accept this input. This bit must
be cleared and set again to perform another counter latch.
Bit 0: Global Interrupt Pin Inhibit (GIPI)
0 = Normal Operation. Interrupt pin (
INTB) will toggle low on an unmasked interrupt condition.
1 = Interrupt Inhibit. Interrupt pin (
INTB) is forced high (inactive) when this bit is set.