Datasheet

DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 78 of 305
Figure 9-18. HDLC Message Transmit Example
9.10.3 HDLC-256 Controller
This device has an enhanced HDLC controller that can be mapped into up to 32 time slots, or Sa4 to Sa8 bits (E1
Mode) or the FDL (T1 Mode). This HDLC controller has a 256-byte FIFO buffer in both the transmit and receive
paths. The user can select any specific bits within the time slot(s) to assign to the HDLC-256 controller, as well as
specific Sa bits (E1 Mode)
Reset Transmit
HDLC Controller
(THC.5)
Configure Transmit
HDLC Controller
(THC1,THC2,THBSE,THFC)
TLWM
Interrupt?
Enable TMEND
Interrupt
No Action Required
Work Another Process
Enable TLWM
Interrupt and
Verify TLWM Clear
Read TFBA
N = TFBA[6..0]
Push Message Byte
into Tx HDLC FIFO
(THF)
Last Byte of
Message?
YES
NO
Set TEOM
(THC1.2)
Push Last Byte
into Tx FIFO
Loop N
TMEND
Interrupt?
YES
Read TUDR
Status Bit
TUDR = 1
YES
Disable TMEND Interrupt
Resend Message
Disable TMEND Interrupt
Prepare New
Message
YES
NO
NO
NO
A
A
A