Datasheet

DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 77 of 305
9.10.2 Transmit HDLC-64 Controller
9.10.2.1 FIFO Information
The Transmit HDLC FIFO Buffer Available Register (
TFBA) indicates the number of bytes that can be written into
the transmit FIFO. The count from this register informs the host as to how many bytes can be written into the
transmit FIFO without overflowing the buffer. This is a real-time register. The count shall remain valid and stable
during the read cycle.
9.10.2.2 Transmit HDLC-64 Example
The HDLC status registers in the DS26514 allow for flexible software interface to meet the user’s preferences.
When transmitting HDLC messages, the host can choose to be interrupt driven, or to poll to desired status
registers, or a combination of polling and interrupt processes can be used.
Figure 9-18 shows an example routine
for using the DS26514 HDLC receiver.