Datasheet

DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 74 of 305
9.10 HDLC Controllers
There are two HDLC Controllers available for each port of the DS26514. HDLC-64 is the default HDLC controller,
which is software compatible to the entire TEX series of SCTs. The HDLC-256 controller is available on the
DS26514 beginning with die revision B1. (Note: Older DS26514 die revisions do not have this feature so check
the device errata). The following table describes the features available for each.
Table 9-36. HDLC-64/HDLC-256 Controller Features
HDLC
CONTROLLER
FIFO DEPTH
(BYTES)
MAP TO FDL
MAP TO
Sa BITS
MAP TO
SINGLE DS0
MAP TO
MULTIPLE
DS0s
HDLC-64
64
Yes
Yes
Yes
No
HDLC-256
256
Yes
Yes
Yes
Yes, up to 32
9.10.1 HDLC-64 Controller
This device has an enhanced HDLC controller that can be mapped into a single time slot, or Sa4 to Sa8 bits (E1
Mode) or the FDL (T1 Mode). This HDLC controller has a 64-byte FIFO buffer in both the transmit and receive
paths. The user can select any specific bits within the time slot(s) to assign to the HDLC-64 controller, as well as
specific Sa bits (E1 Mode)
The HDLC-64 controller performs all the necessary overhead for generating and receiving Performance Report
Messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC
controller automatically generates and detects flags, generates and checks the CRC check sum, generates and
detects abort sequences, stuffs and de-stuffs zeros, and byte aligns to the data stream. The 64-byte buffers in the
HDLC-64 controller are large enough to allow a full PRM to be received or transmitted without host intervention.
The registers related to the HDLC are displayed in the following table.
Table 9-37 shows the registers related to the HDLC.
Table 9-37. Registers Related to the HDLC-64
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Receive HDLC-64 Control Register
(RHC)
010h Mapping of the HDLC to DS0 or FDL, Sa Bits
Receive HDLC-64 Bit Suppress
Register (RHBSE)
011h Receive HDLC bit suppression Register
Receive HDLC-64 FIFO Control
(RHFC)
087h
Determines the watermark of the Receive
HDLC FIFO
Receive HDLC-64 Packet Bytes
Available Register (RHPBA)
0B5h
Tells the user how many bytes are available in
the Receive HDLC FIFO
Receive HDLC-64 FIFO Register (RHF)
0B6h
The actual FIFO data
Receive Real-Time Status Register 5
(RRTS5)
0B4h Indicates the FIFO status
Receive Latched Status Register 5
(RLS5)
094h Latched Status
Receive Interrupt Mask 5 (RIM5) 0A4h
Interrupt Mask for interrupt generation for the
Latched Status
Transmit HDLC-64 Control 1(THC1)
110h
Misc Transmit HDLC Control
Transmit HDLC-64 Bit Suppress
(THBSE)
111h
Transmit HDLC Bit Suppress for bits not to be
used
Transmit HDLC-64 Control 2 (THC2) 113h
HDLC to DS0 channel selection and other
control
Transmit HDLC-64 FIFO Control
(THFC)
187h Used to control the Transmit HDLC FIFO
Transmit HDLC-64 Status (TRTS2) 1B1h
Indicates the Real-Time Status of the Transmit
HDLC FIFO
Transmit HDLC-64 Latched Status
191h
Indicates the FIFO status