Datasheet

DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 45 of 305
Table 9-10. RSYNC Input Pin Definitions (GTCR1.GIBO = 0)
PIN
NAME
NORMAL USE 4.096MHz IBO 8.192MHz IBO 16.384MHz IBO
RSYNC1
Rx Frame Pulse for
port # 1
Rx Frame Pulse for
Ports 1 & 2
Rx Frame Pulse for
Ports 1, 2, 3, & 4
Rx Frame Pulse for
Ports 1, 2, 3, & 4
RSYNC2
Rx Frame Pulse for
port # 2
Unused Unused Unused
RSYNC3
Rx Frame Pulse for
port # 3
Rx Frame Pulse for
Ports 3 & 4
Unused Unused
RSYNC4
Rx Frame Pulse for
port # 4
Unused Unused Unused
9.8.3 H.100 (CT Bus) Compatibility
The H.100 (or CT bus) is a synchronous, bit-serial, TDM transport bus operating at 8.192MHz. The H.100 standard
also allows compatibility modes to operate at 2.048MHz, 4.096MHz, or 8.192MHz. The control bit H100EN
(
RIOCR.5), when combined with RSYNCINV and TSSYNCINV, allows the DS26514 to accept a CT-bus-
compatible frame-sync signal (CT_FRAME) at the RSYNCn and TSSYNCIOn (input mode) inputs. See
Figure 9-14
and
Figure 9-15.
The following rules apply to the H100EN control bit:
1) The H100EN bit controls the sampling point for the RSYNCn (input mode) and TSSYNCIOn (input
mode) only. The RSYNCn output and other sync signals are not affected.
2) The H100EN bit would always be used in conjunction with the receive and transmit elastic store
buffers.
3) The H100EN bit would typically be used with 8.192MHz IBO mode, but could also be used with
4.096MHz IBO mode or 2.048MHz backplane operation.
4) The H100EN bit in RIOCR controls both RSYNCn and TSSYNCIOn (i.e., there is no separate control
bit for the TSSYNCIOn).
5) The H100EN bit does not invert the expected signal; RSYNCINV (
RIOCR) and TSSYNCINV (TIOCR)
must be set high to invert the inbound sync signals.