Datasheet

DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 260 of 305
Register Name:
TH256SRIE
Register Description:
Transmit HDLC-256 Status Register Interrupt Enable
Register Address:
1508h + (20h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
--
--
TFOIE
TFUIE
TPEIE
--
TFEIE
THDAIE
Default
0
0
0
0
0
0
0
0
Bit 5: Transmit FIFO Overflow Interrupt Enable (TFOIE) – This bit enables an interrupt if the TFOL bit is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 4: Transmit FIFO Underflow Interrupt Enable (TFUIE) – This bit enables an interrupt if the TFUL bit is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 3: Transmit Packet End Interrupt Enable (TPEIE) – This bit enables an interrupt if the TPEL bit is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 2: Transmit FIFO Full Interrupt Enable (TFFIE) – This bit enables an interrupt if the TFFL bit is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 1: Transmit FIFO Empty Interrupt Enable (TFEIE) – This bit enables an interrupt if the TFEL bit is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 0: Transmit HDLC Data Available Interrupt Enable (THDAIE) – This bit enables an interrupt if the THDAL bit
is set.
0 = interrupt disabled
1 = interrupt enabled
10.8.2 Receive HDLC-256 Register Definitions
Table 10-31. Receive Side HDLC-256 Register Map
ADDRESS
REGISTER
REGISTER DESCRIPTION
1510h
RH256CR1
Receive HDLC-256 Control Register 1
1511h
RH256CR2
Receive HDLC-256 Control Register 2
1512h
--
Unused
1513h
--
Unused
1514h
RH256SR
Receive HDLC-256 Status Register
1515h
--
Unused
1516h
RH256SRL
Receive HDLC-256 Status Register Latched
1517h
Unused
1518h
RH256SRIE
Receive HDLC-256 Status Register Interrupt Enable
1519h
--
Unused
151Ah
--
Unused
151Bh
--
Unused
151Ch
RH256FDR1
Receive HDLC-256 FIFO Data Register 1
151Dh
RH256FDR2
Receive HDLC-256 FIFO Data Register 2
151Eh
--
Unused
151Fh
--
Unused