Datasheet

DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 259 of 305
Register Name:
TH256SR1
Register Description:
Transmit HDLC-256 Status Register 1
Register Address:
1504h + (20h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
--
--
--
--
--
TFF
TFE
THDA
Bit 2: Transmit FIFO Full (TFF) – When 0, the Transmit FIFO contains 255 or less bytes of data. When 1, the
Transmit FIFO is full.
Bit 1: Transmit FIFO Empty (TFE) – When 0, the Transmit FIFO contains at least one byte of data. When 1, the
Transmit FIFO is empty.
Bit 0: Transmit HDLC Data Storage Available (THDA) – When 0, the Transmit FIFO has less storage space
available in the Transmit FIFO than the Transmit HDLC data storage available level (TDAL[4:0]). When 1, the
Transmit FIFO has the same or more storage space available than the Transmit FIFO HDLC data storage available
level.
Register Name:
TH256SR2
Register Description:
Transmit HDLC-256 Status Register 2
Register Address:
1505h + (20h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
--
--
TFFL5
TFFL4
TFFL3
TFFL2
TFFL1
TFFL0
Bits 5 to 0: Transmit FIFO Fill Level (TFFL[5:0]) – These six bits indicate the number of eight byte groups
available for storage (do not contain data) in the Transmit FIFO. E.g., a value of 21 (15h) indicates the FIFO has
168 (A8h) to 175 (AFh) bytes are available for storage.
Register Name:
TH256SRL
Register Description:
Transmit HDLC-256 Status Register Latched
Register Address:
1506h + (20h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
--
--
TFOL
TFUL
TPEL
--
TFEL
THDAL
Bit 5: Transmit FIFO Overflow Latched (TFOL) – This bit is set when a Transmit FIFO overflow condition occurs.
Bit 4: Transmit FIFO Underflow Latched (TFUL) – This bit is set when a Transmit FIFO underflow condition
occurs. An underflow condition results in a loss of data.
Bit 3: Transmit Packet End Latched (TPEL) – This bit is set when an end of packet is read from the Transmit
FIFO.
Bit 1: Transmit FIFO Empty Latched (TFEL) – This bit is set when the TFE bit transitions from 0 to 1.
Note: This bit is also set when TH256CR1.TFRST is deasserted.
Bit 0: Transmit HDLC Data Available Latched (THDAL) – This bit is set when the THDA bit transitions from 0 to
1. Note: This bit is also set when TH256CR1.TFRST is deasserted.