Datasheet

DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 257 of 305
10.8 HDLC-256 Register Definitions
10.8.1 Transmit HDLC-256 Register Definitions
Table 10-30. Transmit Side HDLC-256 Register Map
ADDRESS
REGISTER
REGISTER DESCRIPTION
1500h
TH256CR1
Transmit HDLC-256 Control Register 1
1501h
TH256CR2
Transmit HDLC-256 Control Register 2
1502h
TH256FDR1
Transmit HDLC-256 FIFO Data Register 1
1503h
TH256FDR2
Transmit HDLC-256 FIFO Data Register 2
1504h
TH256SR1
Transmit HDLC-256 Status Register 1
1505h
TH256SR2
Transmit HDLC-256 Status Register 2
1506h
TH256SRL
Transmit HDLC-256 Status Register Latched
1507h
--
Unused
1508h
TH256SRIE
Transmit HDLC-256 Status Register Interrupt Enable
1509h
--
Unused
150Ah
--
Unused
150Bh
--
Unused
150Ch
--
Unused
150Dh
--
Unused
150Eh
--
Unused
150Fh
--
Unused
Register Name:
TH256CR1
Register Description:
Transmit HDLC-256 Transmit Control Register 1
Register Address:
1500h + (20h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
--
TPSD
TFEI
TIFV
TBRE
TDIE
TFPD
TFRST
Default
0
0
0
0
0
0
0
0
Bit 6: Transmit Packet Start Disable (TPSD) – When 0, the Transmit Packet Processor will continue sending
packets after the current packet end. When 1, the Transmit Packet Processor will stop sending packets after the
current packet end.
Bit 5: Transmit FCS Error Insertion (TFEI) – When 0, the calculated FCS (inverted CRC-16) is appended to the
packet. When 1, the inverse of the calculated FCS (non-inverted CRC-16) is appended to the packet causing a
FCS error. This bit is ignored if transmit FCS processing is disabled (TFPD = 1).
Bit 4: Transmit Inter-frame Fill Value (TIFV) – When 0, inter-frame fill is done with the flag sequence (7Eh).
When 1, inter-frame fill is done with all ‘1’s.
Bit 3: Transmit Bit Reordering Enable (TBRE) – When 0, bit reordering is disabled (The first bit transmitted is the
LSB of the Transmit FIFO Data byte TFD[0]). When 1, bit reordering is enabled (The first bit transmitted is the MSB
of the Transmit FIFO Data byte TFD[7]).
Bit 2: Transmit Data Inversion Enable (TDIE) – When 0, the outgoing data is directly output from packet
processing. When 1, the outgoing data is inverted before being output from packet processing.
Bit 1: Transmit FCS Processing Disable (TFPD) – This bit controls whether or not a FCS is calculated and
appended to the end of each packet. When 0, the calculated FCS bytes are appended to the end of the packet.
When 1, the packet is transmitted without a FCS.
Bit 0: Transmit FIFO Reset (TFRST) – When 0, the Transmit FIFO will resume normal operations, however, data
is discarded until a start of packet is received after RAM power-up is completed. When 1, the Transmit FIFO is