Datasheet

DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 255 of 305
Register Description:
BERT Status Interrupt Mask Register 1
Register Address:
1403h + (10h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
BRA1C BRA0C BRLOSC BSYNCC BRA1D BRA0D
BRLOS
D
BSYNCD
Default
0
0
0
0
0
0
0
0
Bit 7 : Receive All Ones Condition Clear (BRA1C).
0 = interrupt masked
1 = interrupt enabled
Bit 6 : Receive All Zeros Condition Clear (BRA0C).
0 = interrupt masked
1 = interrupt enabled
Bit 5 : Receive Loss Of Synchronization Condition Clear (BRLOSC)
0 = interrupt masked
1 = interrupt enabled
Bit 4 : BERT in Synchronization Condition Clear (BSYNCC).
0 = interrupt masked
1 = interrupt enabled
Bit 3 : Receive All Ones Condition Detect (BRA1D).
0 = interrupt masked
1 = interrupt enabled
Bit 2 : Receive All Zeros Condition Detect (BRA0D).
0 = interrupt masked
1 = interrupt enabled
Bit 1 : Receive Loss Of Synchronization Condition Detect (BRLOSD)
0 = interrupt masked
1 = interrupt enabled
Bit 0 : BERT in Synchronization Condition Detect (BSYNCD).
0 = interrupt masked
1 = interrupt enabled
Register Name:
BLSR2
Register Description:
BERT Latched Status Register 2
Register Address:
1404h + (10h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
-
-
-
-
-
BED
BBCO
BECO
Default
0
0
0
0
0
0
0
0
All latched bits in this register can create interrupts.
Bit 2: BERT Bit Error Detected Event (BED). A latched bit, which is set when a bit error is detected. The receive
BERT must be in synchronization for it to detect bit errors.
Bit 1: BERT Bit Counter Overflow Event (BBCO). A latched bit, which is set when the 32-bit BERT Bit Counter
(BBC) overflows.
Bit 0: BERT Error Counter Overflow Event (BECO). A latched bit, which is set when the 24-bit BERT Error
Counter (BEC) overflows.