Datasheet

DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 254 of 305
Register Name:
BRSR
Register Description:
Bert Real-Time Status Register
Register Address:
1401h + (10h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
- - - - BRA1 BRA0 BRLOS BSYNC
Default
0
0
0
0
0
0
0
0
Bit 3: BERT Receive All-Ones Condition (BRA1). This bit is set when 32 consecutive ones are received and
clears when at least one zero is received.
Bit 2: BERT Receive All-Zeros Condition (BRA0). This bit is set when 32 consecutive zeros are received and
clears when at least one “one” is received.
Bit 1: BERT Receive Loss Of Synchronization Condition (BRLOS). This bit is set whenever the receive BERT
begins searching for a pattern and clears when BERT enter SYNC condition.
Bit 0: BERT in Synchronization Condition (BSYNC). This bit is set when the incoming pattern matches for 32
consecutive bit positions and remains set until the BERT enters Loss of Synchronization condition.
Register Name:
BLSR1
Register Description:
BERT Latched Status Register 1
Register Address:
1402h + (10h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
BRA1C BRA0C BRLOSC BSYNCC BRA1D BRA0D
BRLOS
D
BSYNCD
Default
0
0
0
0
0
0
0
0
All latched bits in this register can create interrupts.
Bit 7: BERT Receive All-Ones Condition Clear (BRA1C). A latched bit, which is set when the BERT transitions
out of All-Ones Condition.
Bit 6: BERT Receive All-Zeros Condition Clear (BRA0C). A latched bit, which is set when the BERT transitions
out of All-Zeros Condition.
Bit 5: BERT Receive Loss Of Synchronization Condition Clear (BRLOSC). A latched bit which is set when the
BERT transitions out of Loss Of Synchronization Condition.
Bit 4: BERT in Synchronization Condition Clear (BSYNCC). A latched bit that is set when the BERT transitions
out of Synchronization Condition.
Bit 3: BERT Receive All-Ones Condition Detect (BRA1D). A latched bit, which is set when 32 consecutive ones
are received.
Bit 2: BERT Receive All-Zeros Condition Detect (BRA0D). A latched bit, which is set when 32 consecutive zeros
are received.
Bit 1: BERT Receive Loss Of Synchronization Condition Detect (BRLOSD). A latched bit which is set
whenever the receive BERT begins searching for a pattern.
Bit 0: BERT in Synchronization Condition Detect (BSYNCD). A latched bit that is set when the incoming pattern
matches for 32 consecutive bit positions.
Register Name:
BSIM1